LIN Bus Controller

The DLIN is soft core of the Local Interconnect Network (LIN) bus controller provides single master with multiple slaves communication concept.
The LIN is a serial communication protocol designed primarity for use in automotive application. Compared to CAN, LIN is a slower but is simplier and more cost efective. It used in applications where events happen in “human time”. It is ideal for communication in intelligent sensors and actuators where the bandwidth and versatility of CAN is not required.
DLIN core provides an interface between a microprocessor/microcontroller and LIN bus. It can work as master or slave LIN node de-pending on work mode determined by microprocessor/microcontroller. The DLIN controller supports transmission speed between 1kb/s and 20kb/s and can transmit and receive LIN messages compatible to LIN 1.3 and LIN 2.1. Reported status information includes the type and condition of transfer operations being performed by the DLIN, as well as wide range of LIN error conditions (overrun, framing, parity, timeout). The DLIN includes programmable timer allows detection of timeout and synchronization error. The core is described at RTL level allowing target use in FPGA andASIC technologies.

LIN (Local Interconnect Network) is a serial communication protocol, which was created to provides a cost efficient bus communication. The LIN standard is developed by LIN consortium (http://www.lin-subbus.org). It includes the specification of the transmission medium, the interface between development tools, the transmission protocol, and the interfaces for software programming. LIN has been created to decrease costs of automotive networks, and replace more expensive CAN in simple application (sensors or actuators). The LIN device can be implemented as a master or as a slave node.


Transmission is initiated by Master Node, which sends the data frame to Slaves Nodes ( maximum 15) throat one wire bus.

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Conforms with LIN 2.1 and LIN 1.3 specification. Automatic LIN Header handling Automatic Re-synchronization Data rate between 1Kbit/s and 20 Kbit/s Master and Slave work mode Time-out detection Extended error detection “Break-in-data” support Available system interface wrappers: AMBA - APB Bus Altera Avalon Bus Xilinx OPB Bus	Automotive, industrial Embedded communication systems

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
addr (2:0)	input	Address bus
datai (7:0)	input	Input data bus
rd	input	Read data strobe
wr	input	Write data strobe
cs	input	Chip select
rxd	input	LIN receive data
datao (7:0)	output	Output data bus
txd	output	LIN transmit data
irq	output	Interrupt signal