DT8051 - Digital Core Design

ALTERA datasheet
XILINX datasheet
ASIC datasheet

OpenMORE rating

Tiny Area High Performance Microcontroller

The DT8051 is area optimized tiny soft core of a single-chip 8-bit embedded microcontroller based on World's fastest and most popular DP8051 core available for over 8 years. DT8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. DT8051 has very low gate count architecture giving 7 150 ASIC gates for complete system including DoCD on-chip debugger. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. DT8051 includes 2-wire DoCD on-chip debugger (TTAG^TM), up to eight external interrupt sources, advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR. DT8051 Core has built in support for the 2-wire TTAG^TM interface - DCD Hardware Debug System called DoCD^TM. This version of debugger is dedicated for applications where number of external pins is limited.
The DT8051 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

Each of the DCD's 8051 Core has built in support for the DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, set breakpoints, watchpoints, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about DCD on Chip Debugger...

100% software compatible with industry standard 8051
Very low gate count, area optimized architecture - 7 150 ASIC gates for complete system including DoCD on-chip debugger
8.1 times faster than standard 80C51 at the same frequency
7.63 VAX MIPS at 100 MHz
Up to 256 bytes of internal (on-chip) Data Memory
Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
Up to 64 kB of external (off-chip) Data Memory
De-multiplexed Address/Data bus to allow easy memory connection
Interface for additional Special Function Registers
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

The following parameters of the DT8051 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.

Internal Program Memory type	synchronous asynchronous
Interrupts	subroutines location
Power Management Mode	used unused
Stop mode	used unused
DoCD^TM debug unit	used unused

Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.

DoCD^TM debug unit
- Processor execution control
- Read-write all processor contents
- Hardware execution breakpoints
- Hardware execution watchpoints
- TTAG 2-wire communication interface
Power Management Unit
- Power management mode
- Switchback feature
- Stop mode
Interrupt Controller
- 2 priority levels
- 8 external interrupt sources
- 3 interrupt sources from peripherals
8-bit I/O Port
- Bit addressable data direction for each line
- Read/write of single line and 8-bit group
Two 16-bit timer/counters
- Timers clocked by internal source
- Auto reload 8-bit timers
- Externally gated event counters
Full-duplex serial port
- 8-bit asynchronous mode, variable baud rate
- 9-bit asynchronous mode, variable baud rate

reset

clk

xdatai (7:0)

xdatao (7:0)

xdataz

xaddress (15:0)

xdatard

xdatawr

xprgrd

xprgwr

port2i (7:0)

port2o (7:0)

int0

int1

int2

int3

int4

int5

int6

int7

prgdatai (7:0)

prgdatao (7:0)

prgaddr (15:0)

prgramwr

sfrdatai (7:0)

sfrdatao (7:0)

sfrwe

sfroe

sfraddr (6:0)

rxd0i

txd0

ttdi

ttdo

ttdoen

ttck

gate0

gate1

stop

pmm

ramdatai (7:0)

ramdatao (7:0)

ramaddr (7:0)

ramoe

ramwe

Pin	Type	Description
reset	input	Global reset
clk	input	Global clock
xdatai (7:0)	input	Data bus from external data/code memory
port2i (7:0)	input	Port 2 input
int0	input	External interrupt 0
int1	input	External interrupt 1
int2	input	External interrupt 2
int3	input	External interrupt 3
int4	input	External interrupt 4
int5	input	External interrupt 5
int6	input	External interrupt 6
int7	input	External interrupt 7
prgdatai (7:0)	input	Data bus from internal program memory
sfrdatai (7:0)	input	Data bus from user SFRs
rxd0i	input	Serial receiver input 0
ttdi	input	DoCD^TM data input
t0	input	Timer 0 input
t1	input	Timer 1 input
gate0	input	Timer 0 gate input
gate1	input	Timer 1 gate input
ramdatai (7:0)	input	Data bus from internal data memory
xdatao (7:0)	output	Data bus for external data/code memory
xdataz	output	External XDATA bus ‘Z’ state
xaddress (15:0)	output	External data/code memory address bus
xdatard	output	External data memory read
xdatawr	output	External data memory write
xprgrd	output	External Program Memory read
xprgwr	output	External Program Memory write
port2o (7:0)	output	Port 2 output
prgdatao (7:0)	output	Output data bus for Internal Program Memory
prgaddr (15:0)	output	Internal Program memory address bus
prgramwr	output	Internal Program Memory write
sfrdatao (7:0)	output	Data bus for user SFRs
sfrwe	output	User SFRs write enable
sfroe	output	User SFRs read
sfraddr (6:0)	output	User SFRs address bus
txd0	output	Serial transmitter output 0
ttdo	output	DoCD^TM data output
ttdoen	output	DoCD^TM data output enable
ttck	output	DoCD^TM data clock
stop	output	Stop mode indicator
pmm	output	Power management mode indicator
ramdatao (7:0)	output	Data bus for internal data memory
ramaddr (7:0)	output	RAM address bus
ramoe	output	Internal data memory read
ramwe	output	Internal data memory write enable

Control Unit

Opcode Decoder

External Memory Interface

xdatai (7:0)

xdatao (7:0)

xdataz

xaddress (15:0)

xdatard

xdatawr

xprgrd

xprgwr

I/O Ports

port2i (7:0)

port2o (7:0)

Interrupt Controller

int0

int1

int2

int3

int4

int5

int6

int7

Program Memory Interface

prgdatai (7:0)

prgdatao (7:0)

prgaddr (15:0)

prgramwr

SFRs Inetrface

sfrdatai (7:0)

sfrdatao (7:0)

sfrwe

sfroe

sfraddr (6:0)

UART0

rxd0i

txd0

DoCD^TM TTAG

ttdi

ttdo

ttdoen

ttck

Timers

gate0

gate1

Power Management Unit

stop

pmm

Internal Data Memory Interface

ramdatao (7:0)

ramaddr (7:0)

ramdatai (7:0)

ramoe

ramwe

ALU

reset

clk

Control Unit

It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.

Opcode Decoder

Performs an instruction opcode decoding and the control functions for all other blocks.

External Memory Interface

Contains memory access related registers like Data Page High (DPH) and Data Page Low (DPL) registers. It performs the memory addressing and data transfers.

I/O Ports

Block contains 8051’s general purpose I/O ports. Each of port’s pin can be read/write as a single bit or as an 8-bit bus.

Interrupt Controller

Interrupt Control module is responsible for the interrupt manage system for the eight external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.

Program Memory Interface

It contains Program Counter (PC) and related logic. It performs the instructions code fetching. Whole program memory (FLASH or SRAM type) can be written by DoCD™ debugger, or application can modify some part of its code - for example storing some data which shouldn’t volatile.

SFRs Inetrface

Special Function Registers interface controls access to externally connected peripherals through SFR bus.

UART0

Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 2 asynchronous modes with variable baudrate covering all standard transmission speeds.

DoCD^TM TTAG

DoCD^TM Debug Unit – it is a 2-wire low gate count real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints controls execution of program memory code; hardware watchpoints can be set and controls internal and external data memories, as well as SFRs. Hardware watchpoints are executed if any write/read occurred at particular address with certain data pattern or without pattern. Two additional pins CODERUN, DEBUGACS indicate the sate of the debugger and CPU. CODERUN is active when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCD™ debugger. The DoCD™ system includes TTAG interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.
Note that TTDI, TTDO, TTDOEN pins are connected together as single bidirectional pin called TTDIO

Timers

System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

Power Management Unit

Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.

Internal Data Memory Interface

Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

ALU

Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation	Speed grade	Utilized Area	Frequency [MHz]
CYCLONE-II	-6	1666⁰ / 1913¹ LC	95⁰ / 90¹
CYCLONE-III	-6	1656⁰ / 1911¹ LC	100⁰ / 95¹
STRATIX-II	-3	1287⁰ / 1507¹ ALUT	155⁰ / 150¹
STRATIX-III	-2	1289⁰ / 1508¹ ALUT	210⁰ / 200¹

DT8051 without⁰ and with¹ DoCD TTAG debugger - implementation results for ALTERA devices.
Results given for working system with connected SFR, IDATA, CODE and XDATA memories.

⁰ - no DoCD debugger
¹ - compact DoCD version includes processor execution control (run, halt, reset, step); read-write all processor content (PC, SFRs); read-write all processor memories (IDATA, XDATA, CODE memory); FLASH code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints

Implementation	Speed grade	Utilized Area	Frequency [MHz]
SPARTAN-3E	-5	1029 ⁰ / 1172¹ Slices	75⁰ / 75¹
VIRTEX-IIP	-7	1026 ⁰ / 1174¹ Slices	130⁰ / 130¹
VIRTEX-4	-11	1031 ⁰ / 1177¹ Slices	140⁰ / 140¹
VIRTEX-5	-3	579 ⁰ / 625¹ Slices	200⁰ / 200¹

DT8051 without⁰ and with¹ DoCD TTAG debugger - implementation results for XILINX devices.
Results given for working system with connected SFR, IDATA, CODE and XDATA memories.

Implementation	Speed grade	Utilized Area [gates]	Frequency [MHz]
0.25u area	typical	6 000⁰ / 7 530¹	100⁰ / 100¹
0.18u area	typical	5 720⁰ / 7 150¹	130⁰ / 130¹

DT8051 without⁰ and with¹ DoCD TTAG debugger - implementation results for ASIC devices.
Results given for working system with connected SFR, IDATA, CODE and XDATA memories.

Design	Dhry speed	on-chip CODE RAM/ROM	off-chip CODE	CODE write	IDATA space	XDATA space	XDATA, CODE wait states	DoCD^TM	PMU	Interrupt sources	DPTR	Timers	UART	IO Ports	Compare/ Capture	Watchdog	MDU MDU32	DI2CM	DI2CS	DSPI	DFPMU	DMAC	DCAN
DP8051CPU	14.7	64k/64k	64k/8M	+	256	16M	+	+	+	2	1	-	-	-	-	-	-	-	-	-	-	-	-
DP8051	14.7	64k/64k	64k/8M	+	256	16M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DP8051XP	14.7	64k/64k	64k/8M	+	256	16M	+	+	+	15	2	3	2	4	+	+	+	+	+	+	+	+	+
DP80C51	11.4	64k/64k	64k	+	256	64k	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DT8051	8.1	64k/64k	64k	+	256	64k	-	+	+	11	1	2	1	1	-	-	-	-	-	-	-	-	-

The main features of each DCD's DP8051, DP80C51, DT8051 family member have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed above and the others) and requests the core modifications. The Core Wizard allows the users to generate their own IP Core.

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Tiny Area High Performance Microcontroller

Control Unit

Opcode Decoder

External Memory Interface

I/O Ports

Interrupt Controller

Program Memory Interface

SFRs Inetrface

UART0

DoCDTM TTAG

Timers

Power Management Unit

Internal Data Memory Interface

ALU

DoCD^TM TTAG