8-bit FAST Microcontroller

The DF6811K is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6811K soft core is binary-compatible with the industry standard Motorola 68HC11K 8-bit microcontroller, and has improved FAST architecture that is ca. 4 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral functions.
The Core can be provided in configurations equivalent to the:

• - MC68HC11K0,
• - MC68HC11K1,
• - MC68HC11K4,
• - MC68HC711K4,
• - MC68HC11KS2,
• - MC68HC711KS2 Microcontrollers

There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811K IP Core especially attractive for automotive and battery-driven applications.
The DF6811K Microcontroller Core can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standerd ADC software. The ADC Controller makes external ADC's visible as internal ADC's in original 68HC11K Microcontrollers. The DF6811K has built in real time hardware on chip debugger the DoCD^TM , allowing easy software debugging and validation. The DF6811K is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each of the DCD's DF68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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FAST architecture, 4 times faster than the original implementation Software compatible with industry standard 68HC11 10 times faster multiplication 16 times faster division 256 bytes of remapped System Function Registers space (SFRs) De-multiplexed Address/Data Bus to allow easy memory connection Core can also be used without I/O wrapper, so each peripheral functions pins will be separated from I/O ports lines. Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories. Fully synthesizable Static synchronous design No internal reset generator or gated clock Positive edge clocking and no internal tri-states Scan test ready 1 GHz of virtual clock frequency compared to original implementation One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode The following parameters of the DF6811K core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. DoCDTM debug unit used unused Memories type synchronous asynchronous Internal Data memory size 0-64kB Internal Program memory size 0-64kB Memories WAIT states used unused Interrupt controller used unused Power saving STOP Mode used unused Besides mentioned above parameters all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface 8-10 8-bit I/O Ports Enhanced Interrupt Controller Pulse Width Modulator (PWM) Four 8-Bit or two 16-Bit PWM Channels Memory Expansion Unit and Chip Selects Six address extension lines Four external Chip Select lines Main16-bit timer/counter system 16 bit free running counter Four stage programmable prescaller Timer clocked by internal source Real Time Interrupt 16-bit Compare/Capture Unit Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring 8-bit Pulse accumulator Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise,Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Mode fault error Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies Interrupt generation Floating Point Coprocessor MDU - Multiply Divide Unit I2C - Master/Slave Interface CAN Bus Controller LIN Bus Controller Ethernet Controller

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
xirq	input	Non-maskable interrupt request
irq	input	Maskable interrupt request
porte (7:0)	input	8-bit Input Port shared with ADC Controller - when enabled.
adcdatai	input	Serial ADC data input
esi	input	Serial Data input - connected to data output pin on EEPROM memory
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
modb	input	Mod B input
ready	input	Ready input to allow operations with slow memories and peripherals
porta (7:0)	output	8 Bit I/O shared with Main Timer syatem: Pulse Accumulator, Input Capture and Ooutput Compare lines
portb (7:0)	output	8-Bit output port, shared with Address bus (15:8)
portc (7:0)	output	GP I/O Port shared with Data Bus.
portd (7:0)	output	GP I/O Port shared with SPI and SCI functions.
portf (7:0)	output	8-bit output port, shared with Address Bus - (7:0)
portg (7:0)	output	GP I/O Port shared with Memory Expansion Unit (MEU)
porth (7:0)	output	GP I/O Port shared with Chip Select Unit and PWM
portj* (7:0)	output	GP I/O Port shared with Timer 2 functions. Available in D68HC11KW1 only.
portk* (7:0)	output	GP I/O Port shared with Timer 3 functions. Available in D68HC11KW1 only.
adcdatao	output	Serial ADC data output
adcclock	output	Serial clock to ADC devices
adccs	output	Serial ADC chip select line
eso	output	Serial data output - connected to data input on EEPROM Memory
esck	output	EEPROM SPI Clock line
ecs	output	EEPROM Chip Select
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
moda_lir	output	Mode A input shared with LIR signal
halt	output	HALT signal used to stop CLock generator during the STOP instrcution execution
rw	output	Read/Write output to external memories