Documentation
 ALTERA datasheet 
 XILINX datasheet 
 LATTICE datasheet 
 ASIC datasheet 
Products Summary
DFPMUL

Floating Point Pipelined Multiplier Unit


The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE-754 standard. The DFPMUL supports a single precision real number. Multiply operation was pipelined up to 7 levels. Input data are fed every clock cycle. The first result appears after latency depending on pipeline level and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included.
The DFPMUL is a technology independent design that can be implemented in a variety of process technologies.

Key Features

Applications

  • Full IEEE-754 compliance
  • Single precision real format support
  • Simple interface
  • No programming required
  • 7 levels pipeline
  • Overflow, underflow and invalid operation flags
  • Full accuracy and precision
  • Results available at every clock
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Math coprocessors
  • DSP algorithms
  • Embedded arithmetic coprocessor
  • Fast data processing & control

Symbol

 clk
 rst
 en
 adatai (31:0)
 bdatai (31:0)
datao (31:0) 
ofo 
ufo 
ifo 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
eninputEnable computing
adatai (31:0)inputA data bus input
bdatai (31:0)inputB data bus input
datao (31:0)outputData bus output
ofooutputOverflow flag
ufooutputUnderflow flag
ifooutputInvalid flag

Block diagram

Main FP Pipelined Unit
Arguments Checker
adatai (31:0)
bdatai (31:0)
Result Composer
datao (31:0)
ofo
ufo
ifo
clk
rst
en

Units

Main FP Pipelined Unit

It performs floating point multiply function. Gives the complex information about the results and makes final flags settings.

Arguments Checker

It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.

Result Composer

It performs floating point to integer conversion. Gives the complex information about the results to Result Composer module.

Performance


Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

ImplementationSpeed
grade		Utilized Area
[LC]		Frequency
[MHz]
APEX20KC-7121051
STRATIX-5440+8M193
CYCLONE-6117072
STRATIX II-3410+8M1134
CYCLONE-II-6480+8M1117

1- 9-bit DSP bock
DFPMUL implementation results for ALTERA devices. The all features have been included.

ImplementationSpeed
grade		Utilized Area
[Slices]		Frequency
[MHz]
SPARTAN-IIE-748857
SPARTAN-3-5222+4M176
SPARTAN-3E-4222+4M167
VIRTEX-E-852060
VIRTEX-II-6222+4M198
VIRTEX-II pro-7222+4M1115
VIRTEX-4-12255+4M2183

1- MULT18X18 block
2- DSP48 block
DFPMUL implementation results for XILINX devices. The all features have been included.

ImplementationSpeed
grade		Utilized Area
[LUT/PFU]		Frequency
[MHz]
ispXPGA-41472/58044
EC-51800/ -45
ECP-51244/ -59

DFPMUL implementation results for LATTICE devices. The all features have been included.

Family summary

DesignStandard complianceOperationInput dataOutput dataNORMAL numbersDENORMAL, NaNs, INFINITYPipeline levelsSingle clock resultInitial latency
DFPADDIEEE-754AdditionSingle precision realSingle precision real++5+5
DFPMULIEEE-754MultiplicationSingle precision realSingle precision real++7+7
DFPDIVIEEE-754DivisionSingle precision realSingle precision real++15+15
DFPSQRTIEEE-754Square rootSingle precision realSingle precision real++9+9
DFPCOMPIEEE-754CompareSingle precision realSingle precision real++1+1
DFP2INTIEEE-754FP to Integer conversionSingle precision realInteger++2+2
DINT2FPIEEE-754Integer to FP conversionIntegerSingle precision real++3+3


The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. Please see also the Arithmetic Coperocessors: DFPMU, and DFPAU