8-bit RISC Microcontroller

The DFPIC165X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast memory (typically on-chip). The core has been designed with a special concern about low power consumption.
The DFPIC165X is a software compatible with the industry standard PIC16C54, PIC16C55, PIC16C56, PIC16C57 and PIC16C58. It employs a modified RISC architecture (2 times faster than original implementation).
The DFPIC165X have enhanced core features and configurable hardware stack. The separate instruction and data buses allow a 12 bit wide instruction word with the separate 8-bit wide data. The DFPIC165X typically achieve a 2:1 code compression and a 8:1 speed improvement over other 8-bit microcontrollers in its class. The Core has 24 I/O lines and an 8-bit timer/counter with an 8-bit programmable prescaller.
The power-down mode SLEEP allow user to reduce power consumption. User can "wake up" the controller from SLEEP through an user reset or watchdog overflow. An integrated Watchdog Timer with it's own clock signal provides protection against software lock-up.
The DFPIC165X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices make this IP core perfect for applications with space and power consumption limitations.
The DFPIC165X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

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Software compatible with industry standard PIC16C5X Harvard RISC architecture 2 times faster compared to original implementation 33 instructions 12 bit wide instruction word Up to 256 bytes of internal Data Memory Up to 4K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready Technology independent HDL Source Code The following parameters of the DFPIC165X core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. RAM memory type synchronous asynchronous RAM size up to 256 B default 128 B Program Memory size up to 4k Words default 2k Number of hardware stack levels 1-8 default 2 SLEEP mode used unused Besides mentioned above parameters all available peripherals can be excluded from the core by changing appropriate constants in package file.

Three 8 bit I/O ports Three 8-bit corresponding TRIS registers Timer 0 8-bit timer/counter Readable and Writable 8-bit software programmable prescaler Internal or external clock select Edge select for external clock Watchdog Timer Configurable Time out period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input

Pin	Type	Description
clk	input	Global clock
por	input	Global reset Power On Reset
mclr	input	User reset
prgdata (11:0)	input	Data bus from program memory
portai (7:0)	input	Port A input
portbi (7:0)	input	Port B input
portci (7:0)	input	Port C input
ramdatai (7:0)	input	Data bus from int. data memory
t0cki	input	Timer 0 input
clkwdt	input	Watchdog clock
sleep	output	Sleep signal
prgaddr (11:0)	output	Program memory address bus
portao (7:0)	output	Port A output
portbo (7:0)	output	Port B output
portco (7:0)	output	Port C output
trisa (7:0)	output	Data direction pins for Port A
trisb (7:0)	output	Data direction pins for Port B
trisc (7:0)	output	Data direction pins for Port C
ramdatao (7:0)	output	Data bus for internal data memory
ramaddr (7:0)	output	RAM address bus
ramwe	output	Data memory write
ramoe	output	Data memory output enable