D8254 - Digital Core Design

ALTERA datasheet
XILINX datasheet
LATTICE datasheet
ASIC datasheet

OpenMORE rating

Programmable Interval Timer

The D8254 is a programmable interval timer/counter, binary compatible with industry standard 82C54. The D8254 solves one of the most common problems in any micro-computer system, the generation of accurate time delays under software control. The D8254 can be used as a:

Real time clock
Even counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller

The D8254 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The D8254 is a technology independent design that can be implemented in a variety of process technologies.


Three independent 16-bit counters Six programmable Counter modes Interrupt on terminal count Hardware retriggerable One-Shot Rate Generator Square wave mode Software triggered strobe Hardware triggered strobe Binary or BCD counting Status Read Back Command Simple interface allows easy connection to microcontrollers Fully synthesizable Static design and no internal tri-states	Embedded microprocessor boards

datai (7:0)

datao (7:0)

rst

addr (1:0)

clk0

gate0

out0

clk1

gate1

out1

clk2

gate2

out2

Pin	Type	Description
datai (7:0)	input	Processor data bus (input)
rst	input	Global reset
cs	input	Chip select
addr (1:0)	input	Processor address lines
rd	input	Processor read strobe
wr	input	Processor write strobe
clk0	input	Clock input for Counter 0
gate0	input	Gate input for Counter 0
clk1	input	Clock input for Counter 1
gate1	input	Gate input for Counter 1
clk2	input	Clock input for Counter 2
gate2	input	Gate input for Counter 2
datao (7:0)	output	Processor data bus (output)
out0	output	Output of Counter 0
out1	output	Output of Counter 1
out2	output	Output of Counter 2

Control Word

Data Bus Buffer

datai (7:0)

datao (7:0)

Read Write Logic

rst

addr (1:0)

Counter 0

clk0

gate0

out0

Counter 1

clk1

gate1

out1

Counter 2

clk2

gate2

out2

Control Word

The Control Word Register is selected by the Read/Write Logic when ADDR(1:0) = 11. If the CPU then does a write operation to the D8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.

Data Bus Buffer

The 8-bit buffer is used to interface the D8254 to the system bus.

Read Write Logic

The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8254. ADDR(1:0) select one of the three counters or the Control Word Reg-ister to be read from/written into. A "low'' on the RD input tells the D8254 that the CPU is reading one of the counters. A "low'' on the WR input tells the D8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low. The WR and CLK signals should be synchronous. This is accomplished by using a CLK input signal to the D8254 counters which is a derivative of the system clock source. Another technique is to externally synchronize the WR and CLK input signals. This is done by gating WR with CLK.

Counter 0

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Counter 1

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Counter 2

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation	Speed grade	Utilized Area [LC]	Frequency [MHz]
APEX20KC	-7	511	129
CYCLONE	-6	510	150
CYCLONE-II	-6	512	238
CYCLONE-III	-6	512	220
STRATIX	-5	512	181
STRATIX-II	-3	512	185
STRATIX-III	-2	510	180
STRATIX-GX	-5	510	166

D8254 implementation results for ALTERA devices. All features have been included.

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-IIE	-7	364	90
SPARTAN-III	-5	364	125
SPARTAN-IIIE	-4	376	80
VIRTEX-E	-8	364	101
VIRTEX-II	-6	364	174
VIRTEX-II pro	-7	367	213
VIRTEX-IV	-12	364	239

D8254 implementation results for XILINX devices. All features have been included.

Implementation	Speed grade	Utilized Area [LUT/PFU]	Frequency [MHz]
EC	-5	527 / 249	72
ECP	-5	527 / 249	70
XP	-5	527 / 249	62

D8254 implementation results for LATTICE devices. All features have been included.

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