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Pipelined High Performance Configurable Microcontroller
The DP8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051XP: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051XP has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.45 to 14.73 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion. The DP8051XP is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.
Each of the DCD's 8051 Core has built in support for the DCD Hardware Debug System called DoCDTM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). In contrast to other on-chip debuggers the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about DCD on Chip Debugger...
 reset clk iprgramsize (2:0) iprgromsize (2:0) t0 t1 gate0 gate1 rxd0irxd0o
txd0
capture0 capture1 capture2 capture3 t2 t2ex scli sdaisclo
sclhs
sdao
tdi tck tmstdo
rtck
port0i (7:0) port1i (7:0) port2i (7:0) port3i (7:0)port0o (7:0)
port1o (7:0)
port2o (7:0)
port3o (7:0)
ramdatai (7:0)ramdatao (7:0)
ramaddr (7:0)
ramoe
ramwe
int0 int1 int2 int3 int4 int5 int6 xdatai (7:0) readyxdatao (7:0)
xdataz
xaddr (23:0)
 xprgrd
xprgwr
xdatard
xdatawr
sfrdatai (7:0)sfrdatao (7:0)
sfrwe
sfroe
sfraddr (6:0)
rxd1irxd1o
txd1
prgramdata (7:0) prgromdata (7:0)prgaddr (15:0)
prgdatao (7:0)
prgramwr
stop
pmm
ssmosi
miso
sck
sso (7:0)
rxclk rxdv rxer rxdata (3:0) qmr (7:0) txclk crs col qmt (7:0) mdidmr (7:0)
waddrmr (10:0)
raddrmr (10:0)
enrmr
enwmr
txdata (3:0)
txen
txer
dmt (7:0)
waddrmt (10:0)
raddrmt (10:0)
enrmt
enwmt
mdo
mdc
mdoe
sxdmdatai (7:0)sxdmaddr (15:0)
sxdmdatao (7:0)
sxdmoe
sxdmwe
iprgramsize (2:0)
iprgromsize (2:0)
 t0t1gate0gate1
rxd0irxd0otxd0
capture0
capture1
capture2
capture3
t2
t2ex
sclisdaisclosclhssdao
tdi
tck
tms
tdo
rtck
port0i (7:0)
port1i (7:0)
port2i (7:0)
port3i (7:0)
port0o (7:0)
 port1o (7:0)
port2o (7:0)
port3o (7:0)
ramdatao (7:0)ramaddr (7:0)ramdatai (7:0)ramoeramwe
int0int1int2int3int4int5int6
xdatai (7:0)
xdatao (7:0)
xdataz
xaddr (23:0)
 ready
xprgrd
xprgwr
xdatard
xdatawr
sfrdatai (7:0)sfrdatao (7:0)sfrwesfroesfraddr (6:0)
rxd1i
rxd1o
txd1
prgramdata (7:0)
prgromdata (7:0)
prgaddr (15:0)
prgdatao (7:0)
prgramwr
stoppmm
mosi
miso
ss
sck
sso (7:0)
rxclk
rxdv
rxer
rxdata (3:0)
qmr (7:0)
dmr (7:0)
waddrmr (10:0)
raddrmr (10:0)
enrmr
enwmr
txclk
crs
col
txdata (3:0)
txen
txer
qmt (7:0)
dmt (7:0)
waddrmt (10:0)
raddrmt (10:0)
enrmt
enwmt
mdo
mdc
mdoe
mdi
sxdmdatai (7:0)sxdmaddr (15:0)sxdmdatao (7:0)sxdmoesxdmwe
reset
 clk
Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.Opcode DecoderPerforms an instruction opcode decoding and the control functions for all other blocks.TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.UART0Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).Compare Capture UnitThe compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing such as pulse generation, pulse width modulation, measurements etc.Timer 2Timer 2 – Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit if it’s presented in system. It can be used as clock source for UART0.Slave I2C UnitI2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver depending on working mode determined by a master device. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs.Master I2C UnitI2C bus controller is a Master module. The core incorporates all features required by I2C specification. Supports both 7-bit and 10-bit addressing modes on the I2C bus. It works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization to allow it operate in multi-master systems. Built-in timer allows operation from a wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs.DoCDTM JTAGDoCDTM Debug Unit – it is a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and con-trolled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoints can be set and controlled on program memory, hardware watchpoints can be set and controlled on internal and external data memories, as well as on SFRs. Hardware watchpoints are executed if any write/read occurred at particular address with certain data pattern or without pattern. Two additional pins CODERUN, DEBUGACS indicate the sate of the debugger and CPU. CODERUN is active when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCD™ debugger. The DoCD™ system includes JTAG interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.ALUArithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.I/O PortsBlock contains 8051’s general purpose I/O ports. Each of port’s pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3.Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.Extended Interrupt ControllerInterrupt Controller module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.External Memory InterfaceExternal Memory Interface contains memory access related registers such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories.SFRs InetrfaceSpecial Function Registers interface controls access to externally connected peripherals through SFR bus.UART1Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF1 loads the transmit register, and reading SBUF1 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.Watchdog TimerThe watchdog timer is a 27-bit counter which is incremented every system clock periods (CLK pin). It performs system protection against software upsets.Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.Floating Point Math UnitFPAU contains floating point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm a full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written pro-grams.SPI UnitIt’s a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.MDU - Multiply Divide UnitMultiply Divide Unit – It’s a fixed point fast 16-bit and 32-bit multiplication and division unit. It provides shift and normalize operations, additionally. All operations are performed using unsigned integer numbers. The MDU contains MD0 to MD5 operands, the result registers and one control register called ARCON. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written programs.DMAC - 10/100 Mb Media Access ControllerThe DMAC is hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting and receiving Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in variety of process technologies. This core strictly conforms to IEEE 802.3 standard.SXDM interfaceSynchronous eXternal Data Memory (SXDM) Interface – contains XDATA memory access related logic allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables frequently accessed by CPU, improving overall performance of application.MDU32 - 32-bit Multiply Divide UnitIt is a fixed point fast 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2's complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers are automatically read and written back by internal DMA. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
DP8051XP implementation results for ALTERA devices - results given for working system
DP8051XP implementation results for XILINX devices - results given for working system
DP8051XP implementation results for LATTICE devices - results given for working system
DP8051XP implementation results for ASIC devices - results given for working system
The main features of each DCD's DP8051, DP80C51, DT8051 family member have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed above and the others) and requests the core modifications. The Core Wizard allows the users to generate their own IP Core. |
