8-bit FAST Microcontrollers Family

The DF6808 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The DF6808 soft core is binary-compatible with the industry standard Motorola 68HC08 8-bit microcontroller and can achieve a performance 45-100 million instructions per second.
The DF6808 has FAST architecture that is 3.2 times faster compared to original implementation. The Core in standard configuration has integrated on chip major peripheral functions.
The DF6808 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI), and the Synchronous Serial Peripheral Interface (SPI).
The main 16-bit, free-running timer system has two input capture lines, and two output-compare lines.
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6808 IP Core especially attractive for automotive and battery-driven applications.
DF6808 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each DCD's DF68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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FAST architecture, 3.2 times faster than the original implementation Software compatible with industry standard 68HC08 Configurable Harvard or Von Neumann architectures 11 times faster multiplication 64 bytes of System Function Registers space (SFRs) Up to 64K bytes of Data Memory Up to 64K bytes of Code Memory De-multiplexed Address/Data Bus to allow easy memory connection Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories. Fully synthesizable Static synchronous design No internal reset generator or gated clock Positive edge clocking and no internal tri-states Scan test ready 800 MHz of virtual clock frequency compared to original implementation One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode The following parameters of the DF6808 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. DoCDTM debug unit used unused Memories type synchronous asynchronous Power saving STOP Mode used unused Besides mentioned above parameters all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Four 8-bit I/O Ports Extended Interrupt Controller 7 interrupt sources 7 priority levels Main16-bit timer/counter system 16 bit free running counter Timer clocked by internal source 16-bit Compare/Capture Unit Two independent input-capture functions Two output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Mode fault error Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies Interrupt generation

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
ss	input	SPI slave select
ready	input	READY pin allows CPU to operate with slow program and data memories. HIGH state on READY pin drives CPU to the WAIT state.
prgdata (7:0)	input	Program memory data bus input. (used in Harvard architectue only)
datai (7:0)	input	Data/Program memory data bus input
ufrdatai (7:0)	input	External UFR registers data bus input
irq	input	External interrupt request input
cap2	input	Input capture channel 2 input
cap1	input	Input capture channel 1 input
portai (7:0)	input	Port A input
portbi (7:0)	input	Port B input
portci (7:0)	input	Port C input
portdi (7:0)	input	Port D input
rxd	input	SCI receiver data input
halt	output	Halt clock system during STOP Instruction
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
mosi	output	SPI Master Output - Slave input
miso	output	SPI Master input - Slave output
sck	output	SPI clock line
sso (7:0)	output	Slave Select outputs
prgaddr (15:0)	output	Program memory address bus. (used in Harvard architecture only)
prgoe	output	Program memory output enable.
datao (7:0)	output	Data memory and External UFR registers output data bus
addr (15:0)	output	Data memory address bus
ramwe	output	Data memory write enable
ramoe	output	Data memory output enable
ufraddr (5:0)	output	External UFR registers address bus
ufrwe	output	External UFR registers write enable
ufroe	output	External UFR registers output enable
cmp1	output	Output compare channel 1 output
cmp2	output	Output compare channel 2 output
portao (7:0)	output	Port A output
portbo (7:0)	output	Port B output
portco (7:0)	output	Port C output
portdo (7:0)	output	Port D output
ddra (7:0)	output	Port A data direction control
ddrb (7:0)	output	Port B data direction control
ddrc (7:0)	output	Port C data direction control
ddrd (7:0)	output	Port D data direction control
txd	output	SCI transmitter data output