Configurable CAN Bus Controller

The DCAN is a stand-alone controller for the Controller Area Network (CAN) widely used in automotive and industrial applications. DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). The Core has simple CPU interface (8/16/32 bit configurable data width) with little or big endian adressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies.

The Controller Area Network (CAN) is a advanced serial communications protocol developed by Robert Bosch GmbH. CAN protocol uses Data Link Layer and the Physical Layer in the ISO-OSI model. The CAN bus uses multi-master bus scheme with one logic bus line and equal nodes. The number of nodes is not limited by the protocol.

Nodes do not have specific addresses. Instead, message identifiers are used, indicating the message content and priority of message. This also means that multicasting and broadcasting is supported by CAN.

Number of nodes may be changed at run-time without disturbing the communication of the other nodes.
CAN provides sophisticated error detection and error handling mechanisms and, due to differential transmission, high immunity against electromagnetic interference. Frames with errors are automatically retransmitted (except single shot transmission feature implemented in the DCAN core).
Maximum data transfer rate is 1Mbps at maximum 40 m bus length when using a twisted wire pair.
The bus is handled with Carrier Sense Multiple Access / Collision Detection with Non-Destructive Arbitration. This means that collision of messages is avoided by bitwise arbitration without loss of time.
CAN controller is connected to host/CPU and CAN bus transceiver, which directly connects to CAN bus line (2-wire).

For more information about the CAN Bus protocol please see....

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Conforms to Bosch CAN 2.0B Active 8/16/32-bit CPU slave interface with little or big endianess Simple interface allows easy connection to CPU Data rate up to 1 Mbps Hardware message filtering (dual/single filter) 64 byte receive FIFO One transmit buffer No overload frames are generated Normal & Listen Only Mode Single Shot transmission Ability to abort transmission Readable error counters Last Error Code Available system interface wrappers: AMBA - APB Bus Altera Avalon Bus Xilinx OPB Bus Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready

Automotive, industrial Embedded communication systems

Pin	Type	Description
qmr (31:0)	input	RX DPRAM data output - configurable 8, 16, 32 bits wide
rxd	input	CAN receive data
be (3:0)	input	Host byte enable - set accprdig to Data bus size
addr (4:0)	input	Host Address bus
datai (31:0)	input	Host output Data bus - configurable 8, 16, 32 bits wide
rd	input	Read Data strobe
wr	input	Write data strobe
cs	input	Chip select
qmt (31:0)	input	TX DPRAM data output - configurable 8, 16, 32 bits wide
dmr (31:0)	output	RX DPRAM data input
waddrmr (3:0)	output	RX DPRAM write address
raddrmr (3:0)	output	RX DPRAM read address
enrmr	output	RX DPRAM read access
enwmr	output	RX DPRAM write enable
sclk	output	SCLK Clock output
txd	output	CAN Transmit data
int	output	Interrupt request signal
datao (31:0)	output	Host input data bus - configurable 8, 16, 32 bits wide
dmt (31:0)	output	TX DPRAM data input - configurable 8, 16, 32 bits wide
waddrmt (1:0)	output	TXDPRAM write address
raddrmt (1:0)	output	TX DPRAM read address
enrmt	output	TXDPRAM read enable
enwmt	output	TX DPRAM write enable