8-bit Microcontrollers Family

The D68HC11E is synthesisable SOFT Microcontroller IP Core fully compatible to the industry standard Motorola 68HC11E, and can be used as direct replacement for the:

• 68HC11E Microcontrollers
  and older 68HC11E versions:
• 68HC11A and
• 68HC11D

The core in standard configuration has integrated on-chip major peripheral functions. An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system with input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring on-chip circuitry is included to protect the D68HC11E against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the D68HC11E IP Core especially attractive for automotive and battery-driven applications.
The D68HC11E Microcontroller Core can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standerd ADC software. The ADC Controller makes external ADC's visible as internal ADC's in original 68HC11E Microcontrollers.
The D68HC11 has built in real time hardware on chip debugger the DoCD^TM, allowing easy software debugging and validation.
The D68HC11E is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.




Each of the DCD's D68HC11E Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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Cycle compatible with original implementation Software compatible with industry standard 68HC11 I/O Wrapper making it pin compatiblecore SFR registers remapped to any 4KB memory page Two power saving modes: STOP, WAI Fully synthesizable Static synchronous design No internal tri-states Scan test ready One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode ADC Controller EEPROM Controller Memory Expansion Unit and Chip Selects PWM Module Floating Point Coprocessor MDU - Multiply Divide Unit I2C - Master/Slave Interface CAN Bus Controller LIN Bus Controller Ethernet Controller

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Five 8-bit I/O Ports Extended Interrupt Controller 20 interrupt sources 17 priority levels Main16-bit timer/counter system 16 bit free running counter Four stage programmable prescaller Timer clocked by internal source Real Time Interrupt 16-bit Compare/Capture Unit Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring 8-bit Pulse accumulator Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise,Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up 1/8 of system clock Mode fault error Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies Interrupt generation

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
cmf	input	Clock monitor fail reset
porte (7:0)	input	8 bit input port, typically shared with internal ADC
moda_lir	input	MODA pin input shared with LIR output
modb	input	Mode B input
xirq	input	Non-maskable interrupt request
irq	input	Maskable interrupt request
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
adcdatai	input	Serial ADC data input
esi	input	Serial Data input - connected to data output pin on EEPROM memory
porta (7:0)	output	Bidirectional Port A, shared with Timer Output Compare and Input Capture functions
portb (7:0)	output	Bidirectional Port B, shared with high address byte in Expanded mode
portc (7:0)	output	Bidirectional Port C, shared with Low address Byte and Data bus. (Demultiplexed Address/Data bus is also possible)
portd (7:0)	output	Bidirectional Port D, shared with SCi and SPI functions.
strb_rw	output	Strobe B shared with R/W in Expanded Mode
stra_as	output	Strobe A, shared with AS (Address Strobe) in expanded mode
e	output	E Clock output
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
adcdatao	output	Serial ADC data output
adcclock	output	Serial clock to ADC devices
adccs	output	Serial ADC chip select line
eso	output	Serial data output - connected to data input on EEPROM Memory
esck	output	EEPROM SPI Clock line
ecs	output	EEPROM Chip Select