8-bit Microprocessor

The D6802 is a 8-bit MPU IP Core. The D6802 is synthesisable SOFT Microprocessor IP Core fully compatible to the Motorola MC6802, and can be used as direct replacement for the MC6802 Microprocessor.
Two software-controlled power-saving modes, WAIT and HALT, are available to conserve additional power. These modes make the D6802 IP Core especially attractive for automotive and battery-driven applications.
The D6802 has built in real time hardware on chip debugger DoCD^TM, allowing easy software debugging and validation.
The D6802 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each of the DCD's D68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microprocessor. More details about DCD on Chip Debugger...

---

Cycle compatible with original implementation Software compatible with industry standard MC6802 De-multiplexed Address/Data Bus to allow easy memory connection Two power saving modes: HALT, WAIT Fully synthesizable Static synchronous design No internal reset generator or gated clock Scan test ready One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use The following parameters of the D6802 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. DoCDTM debug unit used unused

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
halt	input	Halt clock system
re	input	Internal RAM enable input
mr	input	Memory ready input
iramdatai (7:0)	input	Internal Data memory bus input
xdatai (7:0)	input	External memory bus input
irq	input	Interrupt input
nmi	input	Non-maskable interrupt input
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
ba	output	Bus available output
vma	output	Valid memory address
iramoe	output	Internal Program / Data memory output enable
iramwe	output	Internal Program / Data memory write enable
rw	output	External memory read/write output
addr (15:0)	output	Common address bus
datao (7:0)	output	Data bus output
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line