USB 2.0 Audio Devices Design Platform
The USB 2.0 Audio Design Platform is a complete, integrated solution dedicated to use in USB based Audio Devices like microphone or speakers.
The complete Audio Design Platform includes:
- DUSB2 peripheral controller designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates
- DP8051XP ultra high performance, speed optimized, fully customizable 8051 8-bit microcontroller with built in DoCDTM debug IP core
- Audio Devices software stack optimized for DP8051XP 8-bit CPU
- FPGA board with ready to use, preprogrammed example USB stereo speakers application
- HAD2 – DoCDTM Hardware Assisted Debugger board
- DoCDTM Debug Software
- DoCDTM driver for Keil development software
- DoCDTM driver for IAR development software
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- Full compliance with the USB 2.0 specification
- Full-speed 12 Mbps operation
- High-speed 480 Mbps operation
- Supports UTMI Transceiver Macrocell Interface
- Synchronous RAM interface for FIFOs
- Suspend and resume power management functions
- 100% software compatible with industry standard 8051
- Up to 256 bytes of internal (on-chip) Data Memory
- Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
- Up to 16M bytes of external (off-chip) Data Memory
- User programmable Program Memory Wait States solution for wide range of memories speed
- User programmable External Data Memory Wait States solution for wide range of memories speed
- Allows operation from a wide range of CPU clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Lite design, small gate count and fast operation
- Scan test ready
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- Microphone
- Speakers
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 clkcpu  prgromdata (7:0) prgramdata (7:0) ramdatai (7:0) sfrdatai (7:0) xdatai (7:0) int0 int1
prgaddr (15:0)  prgdatao (7:0) prgramwr ramaddr (7:0) ramdatao (7:0) ramwe ramoe sfraddr (6:0) sfrdatao (7:0) sfrwe sfroe xaddr (23:0) xdatao (7:0) xdataz xprgrd xprgwr xdatard xdatawr
utmiclk utmilinestate (1:0) utmidatai (7:0) utmirxvalid utmirxactive usbrxerror utmitxready
utmiopmode (1:0) utmidatao (7:0) utmitxvalid utmisuspendm utmixcvrselect utmitermselect
sramdatai (7:0) sramdataib (7:0)
sramaddra (13:0) sramaddrb (13:0) sramdataoa (7:0) sramdataob (7:0) sramwea sramweb
| Pin | Type | Description |
| clkcpu | input | CPU clock |
| prgromdata (7:0) | input | Data bus from internal ROM program memory |
| prgramdata (7:0) | input | Data bus from internal RAM program memory |
| ramdatai (7:0) | input | Data bus from internal data memory |
| sfrdatai (7:0) | input | Data bus from user SFR’s |
| xdatai (7:0) | input | Data bus from external memories |
| int0 | input | External interrupt 0 |
| int1 | input | External interrupt 1 |
| utmiclk | input | USB clock |
| utmilinestate (1:0) | input | USB line state |
| utmidatai (7:0) | input | USB parallel data input bus |
| utmirxvalid | input | USB receive valid |
| utmirxactive | input | USB receive active |
| usbrxerror | input | USB receive error |
| utmitxready | input | USB transmit ready |
| sramdatai (7:0) | input | SRAM port A data input bus |
| sramdataib (7:0) | input | SRAM port B data input bus |
| prgaddr (15:0) | output | Internal program memory address bus |
| prgdatao (7:0) | output | Data bus for internal program memory |
| prgramwr | output | Internal program memory write |
| ramaddr (7:0) | output | Internal Data Memory address bus |
| ramdatao (7:0) | output | Data bus for internal data memory |
| ramwe | output | Internal data memory write enable |
| ramoe | output | Internal data memory output enable |
| sfraddr (6:0) | output | Address bus for user SFR’s |
| sfrdatao (7:0) | output | Data bus for user SFR’s |
| sfrwe | output | User SFR’s write enable |
| sfroe | output | User SFR’s output enable |
| xaddr (23:0) | output | Address bus for external memories |
| xdatao (7:0) | output | Data bus for external memories |
| xdataz | output | Turn xdata bus into ‘Z’ state |
| xprgrd | output | External program memory read |
| xprgwr | output | External program memory write |
| xdatard | output | External data memory read |
| xdatawr | output | External data memory write |
| utmiopmode (1:0) | output | USB operational mode |
| utmidatao (7:0) | output | USB parallel data output bus |
| utmitxvalid | output | USB transmit valid |
| utmisuspendm | output | USB suspend |
| utmixcvrselect | output | USB transceiver select |
| utmitermselect | output | USB termination select |
| sramaddra (13:0) | output | SRAM port A address bus |
| sramaddrb (13:0) | output | SRAM port B address bus |
| sramdataoa (7:0) | output | SRAM port A data output bus |
| sramdataob (7:0) | output | SRAM port B data output bus |
| sramwea | output | SRAM port A write enable |
| sramweb | output | SRAM port B write enable |
clkcpu prgromdata (7:0) prgramdata (7:0) ramdatai (7:0) sfrdatai (7:0) xdatai (7:0) int0 int1 prgaddr (15:0)  prgdatao (7:0)  prgramwr  ramaddr (7:0) ramdatao (7:0) ramwe ramoe sfraddr (6:0) sfrdatao (7:0) sfrwe sfroe xaddr (23:0) xdatao (7:0) xdataz xprgrd xprgwr xdatard xdatawr
utmiclk utmilinestate (1:0) utmidatai (7:0) utmirxvalid utmirxactive usbrxerror utmitxready utmiopmode (1:0) utmidatao (7:0) utmitxvalid utmisuspendm utmixcvrselect utmitermselect
sramdatai (7:0) sramdataib (7:0) sramaddra (13:0) sramaddrb (13:0) sramdataoa (7:0) sramdataob (7:0) sramwea sramweb
CPU interfaceThe CPU interface module is clocked by cpuclk clock and manages communication with DP8051XP CPU. In this module are located DUSB2 core configuration and status registers.
DP8051XP CPUUltra high performance, speed optimized 8-bit embedded controller, 100% software compatible with industry standard 8051.
UTMI interfaceThe UTMI interface is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
SRAM interfaceThe SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
EP0Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP1Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation | Speed
grade | Utilized Area
[LC] | Frequency
[MHz]
cpuclk/utmiclk |
| CYCLONE-II | -6 | 4040 | 60/>100 |
| CYCLONE-III | -6 | 4040 | 70/>100 |
| STRATIX-II | -3 | 2750 | 100/>100 |
| STRATIX-III | -2 | 2750 | 110/>100 |
| Arria GX | -6 | 2750 | 80/>100 |
Implementation results of the USB 2.0 Audio Devices Design Platform in ALTERA devices.
| Implementation | Speed
grade | Utilized Area
[Slices] | Frequency
[MHz]
cpuclk/utmiclk |
| SPARTAN-III | -5 | 2390 | 50/>100 |
| SPARTAN-IIIE | -5 | 2390 | 60/>100 |
| VIRTEX-4 | -12 | 2390 | 75/>100 |
| VIRTEX-5 | -3 | 1265 | 90/>100 |
Implementation results of the USB 2.0 Audio Devices Design Platform in XILINX devices.
| Implementation | Speed
grade | Utilized Area
[Slices] | Frequency
[MHz]
cpuclk/utmiclk |
| SC | -7 | 2120 | 100/>100 |
| ECP2 | -7 | 2295 | 80/>100 |
| ECP2M | -7 | 2295 | 70/>100 |
| XP2 | -7 | 2555 | 60/>100 |
Implementation results of the USB 2.0 Audio Devices Design Platform in LATTICE devices.
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