Home
Site map
Contact Us
|
|
 |
 |
 |
 |
 |
8-bit MicrocontrollerThe D6803 is synthesisable SOFT Microcontroller IP Core fully compatible to the Motorola MC6803, and can be used as direct replacement for the MC6803 Microcontrollers. The core in standard configuration has integrated on-chip major peripheral functions. An asynchronous serial communications interface (SCI) is included. The main 16-bit, three- function programmable timer. Software-controlled power-saving mode, WAIT, is available to conserve additional power. This mode make the D6803 IP Core especially attractive for automotive and battery-driven applications. The D6803 has built in real time hardware on chip debugger the DoCDTM, allowing easy software debugging and validation. The D6803 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
Each of the DCD's D6803 Core has built in support for DCD Hardware Debug System called DoCDTM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). In contrast to other on-chip debuggers the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...
port1 (7:0)
 port2 (4:0)
port3 (7:0)
port4 (7:0)
 irqnmi
docddatai
 docddatao
docdclk
clkdocd
clk
 rst
SCIThe SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit and stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag.I/O PortsGeneral Purpose I/O Ports, when enabled the I/O Ports are shared with particular on chip peripherals: SCI and TIMER.Timer with Compare CaptureThe programmable timer is based on free-running 16-bit counter, plus input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. The timer has 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contains the high and low byte of that functional block. Accessing the low byte of a specific timer function allows full control of that function, however, an access of the high byte inhibits that specific timer function until the byte is also accessed.Control UnitControl unit performs the core synchronization and data flow control.Opcode DecoderPerforms an instruction opcode decoding and the control functions for all other blocks.ALUArithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index register X and related logic like arithmetic unit, logic unit, multiplier and divider.Interrupt ControllerInterrupt Controller – Interrupt Control module is responsible for the interrupt manage system for the external & internal interrupts and exceptions processing. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.DoCDTMDoCDTM Debug Unit – it’s a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.The separate DoCDTM clock line allow debugger to operate while the SLEEP mode (major clock line CLK is stopped).
The main features of each D68XX and DF68XX family member have been summarized in table above. It gives a brief member characterization to help selection of the most suitable IP Core for application. User can specify its own peripheral set (including listed above and the others) and request the core modifications. |
