DI2CS-APB - Digital Core Design

ASIC datasheet

I²C Bus Interface - Slave with APB interface

The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS-APB core provides an interface between parallel APB bus and serial I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS-APB core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS-APB supports all the transmission speed modes.
The DI2CS-APB is a technology independent design that can be implemented in a variety of process technologies.

Compliant with AMBA specification, Revision 2.0
Single APB input clock for registers and I2C bus serial clock generation
Conforms to v.3.0 of the I2C specification
Slave operation
- Slave transmitter
- Slave receiver
Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
Allows operation from a wide range of input clock frequencies
Simple interface allows easy connection to existing APB systems
Interrupt generation
User-defined data setup time
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Embedded microprocessor boards
Consumer and professional audio/video
Home and automotive radio
Low-power applications
Communication systems
Cost-effective reliable automotive systems

pclk

presetn

int

sdai

sdao

scli

sclo

pwdata (7:0)

pwrite

penable

psel

paddr (7:0)

prdata (7:0)

Pin	Type	Description
pclk	input	APB global clock
presetn	input	Active low APB global reset
sdai	input	I2C bus data line (input)
scli	input	I²C bus clock line (input)
pwdata (7:0)	input	APB write data bus
pwrite	input	APB write strobe.
penable	input	Indicates the second cycle of APB transfer.
psel	input	APB slave select
paddr (7:0)	input	APB address bus
int	output	Interrupt request
sdao	output	I2C bus data line (output)
sclo	output	I2C bus clock line (output)
prdata (7:0)	output	APB read data bus.

Data Unit

sdai

sdao

Control Logic

Clock Unit

scli

sclo

APB Interface

pwdata (7:0)

prdata (7:0)

pwrite

penable

psel

paddr (7:0)

pclk

presetn

int

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.

Control Logic

Control Logic manages execution of all commands sent via CPU interface. Synchronizes internal data flow.

Clock Unit

It performs I²C SCL clock stretching when DI2CS core is not ready for next transmission. SCLI spikes are filtered by this unit.

APB Interface

APB Interface performs the interface functions between DI2CS internal blocks and APB bus. Allows easy connection of the core to existing APB systems.

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Technology	Speed grade	Utilized Area [gates]	Frequency [MHz]
0.25u area	typical	700	160
0.25u speed	typical	1350	600

The presented above table gives a survey about the DI2CS-APB area and performance in ASIC devices (all features are included).

Design

I2C specification

Operation type

Standard mode

Fast mode

Fast Plus mode

High Speed mode

Multi master

7 bit address

10 bit address

Interrupt gen.

Passive elements interface

Microcontroller interface

User defined timing

100 kb/s

400 kb/s

1 Mb/s

3.4 Mb/s

DI2CM

v. 3.0

MASTER

DI2CS

v. 3.0

SLAVE

DI2CSB

v. 3.0

SLAVE

DI2CMS

v. 3.0

MASTER/SLAVE

The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.

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I2C Bus Interface - Slave with APB interface

Data Unit

Control Logic

Clock Unit

APB Interface

I²C Bus Interface - Slave with APB interface