I²C Bus Interface - Master/Slave with APB interface

The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CMS-APB core provides an interface between parallel APB bus and an I2C bus. It can work as a master or slave transmitter/receiver depending on working mode determined by microprocessor. The DI2CMS-APB core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. The DI2CMS-APB supports all the transmission speed modes. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CMS-APB is a technology independent VHDL or VERILOG design that can be implemented in a variety of process technologies and can be fully customized accordingly to customer needs.
The DI2CMS-APB is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each devices is recognised by a unique address – whether it is a microcontroller, LCD driver, memory or keyboard interface – and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Figure below).

A master is the device which initiates a data transfer on the bus and generates the SCL clock signals. A slave is the device addressed by a master.
The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers or microprocessors.

For more information about the I2C Bus protocol please see....

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Compliant with AMBA specification, Revision 2.0 Single APB input clock for registers and I2C bus serial clock generation Conforms to v.3.0 of the I2C specification Master mode Master operation Master transmitter Master receiver Support for all transmission speeds Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) Arbitration and clock synchronization Support for multi-master systems Support for both 7-bit and 10-bit address-ing formats on the I2C bus Build-in 8-bit timer for data transfers speed adjusting Slave mode Slave operation Slave transmitter Slave receiver Supports 3 transmission speed modes Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) Allows operation from a wide range of input clock frequencies User-defined data setup time User-defined timing (data setup, start setup, start hold, etc.) Interrupt generation Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready

Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems

Pin	Type	Description
pclk	input	APB global clock
presetn	input	Active low APB global reset
sdai	input	I2C bus data line (input)
scli	input	I2C bus clock line (input)
pwdata (7:0)	input	APB write data bus
pwrite	input	APB write strobe
penable	input	Indicates the second cycle of APB transfer
psel	input	APB slave select
paddr (2:0)	input	APB address bus
int	output	Interrupt request
sdao	output	I2C bus data line (output)
sclo	output	I2C bus clock line (output)
sclhs	output	High-speed clock line (output)
prdata (7:0)	output	APB read data bus