16/32-bit Microprocessor

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. The D68000 has a 16-bit data bus and a 24-bit address data bus. It is code compatible with the MC68008 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. The D68000 has improved instructions set allows execution of a program with higher per-formance than standard 68000 core.
The D68000 is delivered with fully automated test-bench and complete set of tests allowing easy package validation at each stage of SoC design flow.

A special testing paltfrom has been built to run D68000 with uCLinux Operating System. For more details please check this link.

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Software compatible with industry standard 68000 MULS, MULU take 28 clock periods DIVS, DIVU take 28 clock periods Optimized shifts and rotations Idle cycles removed to improve performance Shorter effective address calculation time Bus cycle timings identical to 68000 32 bit data and address registers 14 addressing modes: Direct: Data register direct Address register direct Indirect: Register indirect Postincrement register indirect Predecrement register indirect Register indirect with offset Indexed register indirect with offset PC relative: Relative with offset Relative with index and offset Absolute data: Absolute short Absolute long Immediate data: Immediate Quick immediate Implied

5 data types supported: bits BCD bytes, words and long words Arithmetic Logic Unit includes: 8,16,32-bit arithmetic & logical operations 16x16 bit signed and unsigned multiplication 32/16 bit signed and unsigned division Boolean operations Interrupt controller: 7 priority levels interrupt controller Unlimited number of virtual interrupt sources Vectored and auto-vectored modes Memory interface includes: Up to 4 GB of address space 16-bit data bus Asynchronous bus control M6800 family synchronous interface 3- and 2- wire bus arbitration Supervisor and user modes Fully synthesizable Static synchronous design

Pin	Type	Description
clk	input	Global clock
rsti	input	Global reset input
halti	input	Halt input
ipl (2:0)	input	Interrupt control
datai (15:0)	input	Data bus input
dtack	input	Data transfer acknowledge
br	input	Bus request
bgack	input	Bus grant acknowledge
berr	input	Bus error
vpa	input	Valid peripheral address
rsto	output	Reset output
halto	output	Halt output
addr (23:0)	output	Address data bus
datao (15:0)	output	Data bus output
addrz	output	Turns DATA bus into 'Z' state
dataz	output	Turns ADDRESS bus into 'Z' state
fc (2:0)	output	Processor function code
ctrlz	output	Turns AS, RDWR, UDS, LDS, VMA, FC(2:0) into 'Z' state
as	output	Address strobe
lds	output	Lower data byte strobe
uds	output	Upper data byte strobe
rdwr	output	Read write signal
bg	output	Bus grant
vma	output	Valid memory address
epd	output	Enable peripheral device