8-bit FAST Microcontrollers Family

The DF6811 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller, and has improved FAST architecture that is ca. 4 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral functions.
There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications.
The DF6811 has built in real time hardware on chip debugger DoCD^TM, allowing easy software debugging and validation.
The DF6811 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each of the DCD's DF68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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FAST architecture, 4 times faster than the original implementation Software compatible with industry standard 68HC11 10 times faster multiplication 16 times faster division 256 bytes of remapped System Function Registers space (SFRs) De-multiplexed Address/Data Bus to allow easy memory connection Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories. Fully synthesizable Static synchronous design No internal reset generator or gated clock Positive edge clocking and no internal tri-states Scan test ready 1 GHz of virtual clock frequency compared to original implementation One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode The following parameters of the DF6811 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Memories type synchronous asynchronous Internal Data memory size 0-64kB Internal Program memory size 0-64kB Memories WAIT states used unused Interrupt controller used unused Power saving STOP Mode used unused DoCDTM debug unit used unused Besides mentioned above parameters all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCD™ debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Four 8-bit I/O Ports Extended Interrupt Controller 20 interrupt sources 17 priority levels Main16-bit timer/counter system 16 bit free running counter Four stage programmable prescaller Timer clocked by internal source Real Time Interrupt 16-bit Compare/Capture Unit Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring 8-bit Pulse accumulator Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise,Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Mode fault error Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies Interrupt generation Memory Expansion Unit Floating Point Coprocessor MDU - Multiply Divide Unit I2C - Master/Slave Interface

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
cmf	input	Clock monitor fail reset
moda	input	Mode A input
modb	input	Mode B input
irq	input	Interrupt input
xirq	input	Non-maskable interrupt input
ready	input	READY pin allows CPU to operate with slow program and data memories. HIGH state on READY pin drives CPU to the WAIT state.
iramdatai (7:0)	input	Internal RAM memory data
iromdatai (7:0)	input	Internal ROM data bus input
xramdatai (7:0)	input	External memory databus input
ufrdatai (7:0)	input	User Function Register (External SFRs) databus input
cap1	input	Capture input 1
cap2	input	Capture input 2
cap3	input	Capture input 3
rxd	input	SCI receiver data input
si	input	SPI slave input
mi	input	SPI master input
ss	input	SPI slave select
scki	input	SPI clock input
pai	input	Pulse accumulator input
portai (7:0)	input	Port A input
portbi (7:0)	input	Port B input
portci (7:0)	input	Port C input
portdi (7:0)	input	Port D input
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
lir	output	Load instruction register
halt	output	Halt clock system (STOP inst.)
datao (7:0)	output	Data memory & UFR bus output
iramaddr (8:0)	output	Internal RAM address bus
iramwe	output	Internal RAM write enable
iramoe	output	Internal RAM output enable
iromaddr (12:0)	output	Internal ROM address bus
iromwe	output	Internal ROM wroite enable - allows to upload the ROM contents by DoCD Debugger.
iromoe	output	Internal ROM output enable
xramaddr (15:0)	output	External memory address bus
xramwe	output	External memory write enable
xramoe	output	External memory output enable
ufraddr (7:0)	output	User Function Registers (External SFRs) address bus
ufrwe	output	User Function Registers write enable
ufroe	output	User Function Registers output enable
dataen	output	Data bus output enable
cmp1	output	Compare output 1
cmp2	output	Compare output 2
cmp3	output	Compare output 3
cmp4	output	Compare output 4
cmp5	output	Compare output 5
cmp1en	output	Output compare 1 output enable
cmp2en	output	Output compare 2 output enable
cmp3en	output	Output compare 3 output enable
cmp4en	output	Output compare 4 output enable
cmp5en	output	Output compare 5 output enable
txd	output	SCI transmitter data output
so	output	SPI slave output
mo	output	SPI master output
scko	output	SPI clock output
scken	output	SPI clock line tri-state buffer control
sso (7:0)	output	Slave Select outputs
soen	output	SPI slave output enable
portao (7:0)	output	Port A output
portbo (7:0)	output	Port B output
portco (7:0)	output	Port C output
portdo (7:0)	output	Port D output
ddra (7:0)	output	Port A data direction control
ddrb (7:0)	output	Port B data direction control
ddrc (7:0)	output	Port C data direction control
ddrd (7:0)	output	Port D data direction control
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line