DFPDIV - Digital Core Design

ALTERA implementation
XILINX implementation
LATTICE implementation
ASIC implementation

OpenMORE rating

Floating Point Pipelined Divider Unit

The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE-754 standard. The DFPDIV supports a single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy are included.
The DFPADD is a technology independent design that can be implemented in a variety of process technologies.


Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Overflow, underflow and invalid operation flags Full accuracy and precision Results available at every clock Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready	Math coprocessors DSP algorithms Embedded arithmetic coprocessor Fast data processing & control

clk

rst

adatai (31:0)

bdatai (31:0)

datao (31:0)

ofo

ufo

ifo

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
en	input	Enable computing
adatai (31:0)	input	A data bus input
bdatai (31:0)	input	B data bus input
datao (31:0)	output	Data bus output
ofo	output	Overflow flag
ufo	output	Underflow flag
ifo	output	Invalid flag

Main FP Pipelined Unit

Arguments Checker

adatai (31:0)

bdatai (31:0)

Result Composer

datao (31:0)

ofo

ufo

ifo

clk

rst

Main FP Pipelined Unit

It performs floating point divide function. Gives the complex information about the results and makes final flags settings.

Arguments Checker

It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.

Result Composer

It performs floating point to integer conversion. Gives the complex information about the results to Result Composer module.

Implementation	Speed grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	3100	30
ACEX1K	-1	3100	30
APEX20K	-1	2720	40
APEX20KE	-1	2720	40
APEX20KC	-7	2720	42
APEX II	-7	2720	50
MERCURY	-5	2780	65
STRATIX	-5	2270	88
CYCLONE	-6	2270	86
STRATIX II	-3	2040	104
CYCLONE-II	-6	2500	107

DFPDIV implementation results for ALTERA devices. The all features have been included.

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	1410	40
SPARTAN-IIE	-7	1727	73
SPARTAN-3	-5	1728	81
SPARTAN-3E	-4	1728	64
VIRTEX	-6	1410	42
VIRTEX-E	-8	1410	55
VIRTEX-II	-6	1728	115
VIRTEX-II pro	-7	1728	134
VIRTEX-4	-12	1728	166

DFPDIV implementation results for XILINX devices. The all features have been included.

Implementation	Speed grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4	-3	2996/479	27
ispXPGA	-4	3132/1063	41

DFPDIV implementation results for LATTICE devices. The all features have been included.

Design	Standard compliance	Operation	Input data	Output data	NORMAL numbers	DENORMAL, NaNs, INFINITY	Pipeline levels	Single clock result	Initial latency
DFPADD	IEEE-754	Addition	Single precision real	Single precision real	+	+	5	+	5
DFPMUL	IEEE-754	Multiplication	Single precision real	Single precision real	+	+	7	+	7
DFPDIV	IEEE-754	Division	Single precision real	Single precision real	+	+	15	+	15
DFPSQRT	IEEE-754	Square root	Single precision real	Single precision real	+	+	9	+	9
DFPCOMP	IEEE-754	Compare	Single precision real	Single precision real	+	+	1	+	1
DFP2INT	IEEE-754	FP to Integer conversion	Single precision real	Integer	+	+	2	+	2
DINT2FP	IEEE-754	Integer to FP conversion	Integer	Single precision real	+	+	3	+	3

The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. Please see also the Arithmetic Coperocessors: DFPMU, and DFPAU

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