Datasheets
 ALTERA implementation 
 XILINX implementation 
 LATTICE implementation 
 ASIC implementation 
Application Notes Products Summary
DI2CS

I2C Bus Interface - Slave



The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS supports all the transmission speed modes.
The DI2CS is a technology independent design that can be implemented in a variety of process technologies.


Key Features

Applications

  • Conforms to v.3.0 of the I2C specification
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Interrupt generation
  • User-defined data setup time
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems


Symbol

 clk
 rst
 scli
sclo 
 sdai
sdao 
 datai (7:0)
 rd
 we
 address (1:0)
 cs
datao (7:0) 
irq 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
scliinputI2C bus clock line (input)
sdaiinputI2C bus data line (input)
datai (7:0)inputProcessor data bus (input)
rdinputProcessor read strobe
weinputProcessor write strobe
address (1:0)inputProcessor address lines
csinputChip select
sclooutputI2C bus clock line (output)
sdaooutputI2C bus data line (output)
datao (7:0)outputProcessor data bus (output)
irqoutputProcessor interrupt line

Block diagram

Clock Unit
scli
sclo
Control Logic
Data Unit
sdai
sdao
CPU Interface
datai (7:0)
datao (7:0)
rd
we
address (1:0)
cs
irq
clk
rst

Units

Clock Unit

It performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. SCLI spikes are filtered by this unit.

Control Logic

Control Logic manages execution of all commands sent via CPU interface. Synchronizes internal data flow.

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.

CPU Interface

CPU Interface performs the interface functions between DI2CS internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system.

Performance

ImplementationSpeed
grade
Utilized Area
[LC]
Frequency
[MHz]
FLEX10KE-1170107
ACEX1K-1170107
APEX20K-117090
APEX20KE-1170120
APEX20KC-7170150
APEX II-7170270
MERCURY-5170250
STRATIX-5170260
CYCLONE-6170220

DI2CS implementation results for ALTERA devices. The all features have been included.

ImplementationSpeed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
ORCA 3-7141/3156
ORCA 4-3182/3197
ispXPGA-5147/43141
EC-5191/51166
ECP-5191/51167
XP-5191/51148
ECP2-7183/50245
ECP2M-7153/49258
SC-7167/50284
XP2-7153/49220

DI2CS implementation results for LATTICE devices. The all features have been included.

ImplementationSpeed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-II-680112
SPARTAN-IIE-778133
SPARTAN-3-578133
SPARTAN-3E-478127
VIRTEX-680111
VIRTEX-E-880138
VIRTEX-II-680140
VIRTEX-II pro-781264
VIRTEX-4-1281322

DI2CS implementation results for XILINX devices. The all features have been included.


Family summary

DesignI2C specificationOperation typeStandard mode   Fast     modeFast Plus modeHigh Speed modeMulti master7 bit address10 bit addressInterrupt gen.Passive elements interfaceMicrocontroller interfaceUser defined timing
100 kb/s400 kb/s1 Mb/s3.4 Mb/s
DI2CMv. 3.0MASTER++++++++-++
DI2CSv. 3.0SLAVE++++++-+-++
DI2CSBv. 3.0SLAVE++++++--+--
DI2CMSv. 3.0MASTER/SLAVE++++++++-++


The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.