Pipelined High Performance Microcontroller

The DP8051 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
The DP8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051 has a Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times slower than the original implementation without performance depletion.
The DP8051 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.


Each of the DCD's 8051 Core has built in support for the DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about DCD on Chip Debugger...

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100% software compatible with industry standard 8051 Pipelined RISC architecture 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster division Up to 256 bytes of internal (on-chip) Data Memory Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory Up to 16 MB of external (off-chip) Data Memory User programmable Program Memory Wait States User programmable External Data Memory Wait States De-multiplexed Address/Data bus to allow easy memory connection Interface for additional Special Function Registers Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready 2 GHz virtual clock frequency in a 0.35u technological process The following parameters of the DP8051 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Internal Program Memory type synchronous asynchronous Internal Program ROM Memory size 0-64kB Internal Program RAM Memory size 0-64kB Internal Program Memory fixed size true false Interrupts subroutines location Power Management Mode used unused Stop mode used unused DoCDTM debug unit used unused Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.

DoCD™ debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints JTAG communication interface Power Management Unit Power management mode Switchback feature Stop mode Interrupt Controller 2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8-bit group Two 16-bit timer/counters Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters Full-duplex serial port Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate

Pin	Type	Description
reset	input	Global reset
clk	input	Global clock
iprgramsize (2:0)	input	Size of on-chip RAM CODE
iprgromsize (2:0)	input	Size of on-chip ROM CODE
rxd0i	input	Serial receiver input 0
t0	input	Timer 0 input
t1	input	Timer 1 input
gate0	input	Timer 0 gate input
gate1	input	Timer 1 gate input
port0i (7:0)	input	Port 0 input
port1i (7:0)	input	Port 1 input
port2i (7:0)	input	Port 2 input
port3i (7:0)	input	Port 3 input
ramdatai (7:0)	input	Data bus from internal data memory
int0	input	External interrupt 0
int1	input	External interrupt 1
sfrdatai (7:0)	input	Data bus from user SFRs
prgramdata (7:0)	input	Data bus from internal RAM program memory
prgromdata (7:0)	input	Data bus from internal ROM program memory
xdatai (7:0)	input	Data bus from external memories
ready	input	External memory data ready
tdi	input	DoCDTM TAP data input
tck	input	DoCDTM TAP clock line
tms	input	DoCDTM TAP mode select
sxdmdatai (7:0)	input	Data bus from sync external data memory (SXDM)
rxd0o	output	Serial receiver output 0
txd0	output	Serial transmitter output 0
port0o (7:0)	output	Port 0 output
port1o (7:0)	output	Port 1 output
port2o (7:0)	output	Port 2 output
port3o (7:0)	output	Port 3 output
ramaddr (7:0)	output	RAM address bus
ramdatao (7:0)	output	Data bus for internal data memory
ramoe	output	Internal data memory read
ramwe	output	Internal data memory write enable
sfrdatao (7:0)	output	Data bus for user SFRs
sfrwe	output	User SFRs write enable
sfroe	output	User SFRs read
sfraddr (6:0)	output	User SFRs address bus
prgaddr (15:0)	output	Internal program memory address bus
prgdatao (7:0)	output	Data bus for internal program memory
prgramwr	output	Internal program memory write
xdatao (7:0)	output	Data bus for external memories
xdataz	output	Turn xdata bus into ‘Z’ state
xaddr (23:0)	output	Address bus for external memories
xprgrd	output	External program memory read
xprgwr	output	External program memory write
xdatard	output	External data memory read
xdatawr	output	External data memory write
stop	output	Stop mode indicator
pmm	output	Power management mode indicator
tdo	output	DoCDTM TAP data output
rtck	output	DoCDTM return clock
sxdmaddr (15:0)	output	Sync XDATA memory address bus (SXDM)
sxdmdatao (7:0)	output	Data bus for Sync XDATA memory (SXDM)
sxdmoe	output	Sync XDATA memory read (SXDM)
sxdmwe	output	Sync XDATA memory write (SXDM)