Pipelined High Performance Configurable Microcontroller

The DP8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
The DP8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051XP: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051XP has a Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion.
The DP8051XP is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.


Each of the DCD's 8051 Core has built in support for the DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about DCD on Chip Debugger...

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100% software compatible with industry standard 8051 Pipelined RISC architecture 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster division 2 Data Pointers (DPTR) for faster memory blocks copying Advanced INC & DEC modes Auto-switch of current DPTR Up to 256 bytes of internal (on-chip) Data Memory Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory Up to 16 MB of external (off-chip) Data Memory Synchronous eXternal Data Memory (SXDM) Interface User programmable Program Memory Wait States User programmable External Data Memory Wait States De-multiplexed Address/Data bus to allow easy memory connection Interface for additional Special Function Registers Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready 2 GHz virtual clock frequency in a 0.35u technological process The following parameters of the DP8051XP core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Internal Program Memory type synchronous asynchronous Internal Program ROM Memory size 0-64kB Internal Program RAM Memory size 0-64kB Internal Program Memory fixed size true false Second Data Pointer (DPTR1) used unused DPTR0 decrement used unused DPTR1 decrement used unused Data Pointers auto-switch used unused Interrupts subroutines location Timing access protection used unused Power Management Mode used unused Stop mode used unused DoCDTM debug unit used unused Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.

DoCD™ debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints JTAG communication interface Power Management Unit Power management mode Switchback feature Stop mode Extended Interrupt Controller 2 priority levels Up to 7 external interrupt sources Up to 8 interrupt sources from peripherals Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8-bit group Three 16-bit timer/counters Timers clocked by internal source Auto reload 8/16-bit timers Externally gated event counters Two full-duplex serial ports Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Four transfer formats supported System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation Programmable Watchdog Timer 16-bit Compare/Capture Unit Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation & measuring Floating-Point math coprocessor - IEEE-754 standard single precision real, word and short integers FADD, FSUB - addition, subtraction FMUL, FDIV - multiplication, division FSQRT - square root FUCOM - compare FCHS - change sign FABS - absolute value FSIN, FCOS - sine, cosine FTAN, FATAN - tangent, arcs tangent

Pin	Type	Description
reset	input	Global reset
clk	input	Global clock
iprgramsize (2:0)	input	Size of on-chip RAM CODE
iprgromsize (2:0)	input	Size of on-chip ROM CODE
t0	input	Timer 0 input
t1	input	Timer 1 input
gate0	input	Timer 0 gate input
gate1	input	Timer 1 gate input
rxd0i	input	Serial receiver input 0
capture0	input	Timer 2 capture 0 line
capture1	input	Timer 2 capture 1 line
capture2	input	Timer 2 capture 2 line
capture3	input	Timer 2 capture 3 line
t2	input	Timer 2 clock line
t2ex	input	Timer 2 control
scli	input	Master/Slave I2C clock line input
sdai	input	Master/Slave I2C data input
tdi	input	DoCDTM TAP data input
tck	input	DoCDTM TAP clock line
tms	input	DoCDTM TAP mode select
port0i (7:0)	input	Port 0 input
port1i (7:0)	input	Port 1 input
port2i (7:0)	input	Port 2 input
port3i (7:0)	input	Port 3 input
ramdatai (7:0)	input	Data bus from internal data memory
int0	input	External interrupt 0
int1	input	External interrupt 1
int2	input	External interrupt 2
int3	input	External interrupt 3
int4	input	External interrupt 4
int5	input	External interrupt 5
int6	input	External interrupt 6
xdatai (7:0)	input	Data bus from external memories
ready	input	External memory data ready
sfrdatai (7:0)	input	Data bus from user SFRs
rxd1i	input	Serial receiver input 1
prgramdata (7:0)	input	Data bus from internal RAM program memory
prgromdata (7:0)	input	Data bus from internal ROM program memory
si	input	SPI slave input
mi	input	SPI master input
ss	input	SPI slave select
scki	input	SPI clock input
rxclk	input	Ethernet receive clock
rxdv	input	Ethernet receive data valid
rxer	input	Ethernet receive error
rxdata (3:0)	input	Ethernet receive data
qmr (7:0)	input	RX DPRAM data output
txclk	input	Ethernet transmit clock
crs	input	Ethernet carrier sense
col	input	Ethernet collision detection
qmt (7:0)	input	TX DPRAM data output
mdi	input	Management data input
sxdmdatai (7:0)	input	Data bus from sync external data memory (SXDM)
rxd0o	output	Serial receiver output 0
txd0	output	Serial transmitter output 0
sclo	output	Master/Slave I2C clock output
sclhs	output	High speed Master I2C clock line
sdao	output	Master/Slave I2C data output
tdo	output	DoCDTM TAP data output
rtck	output	DoCDTM return clock
port0o (7:0)	output	Port 0 output
port1o (7:0)	output	Port 1 output
port2o (7:0)	output	Port 2 output
port3o (7:0)	output	Port 3 output
ramaddr (7:0)	output	RAM address bus
ramdatao (7:0)	output	Data bus for internal data memory
ramoe	output	Internal data memory read
ramwe	output	Internal data memory write enable
xdatao (7:0)	output	Data bus for external memories
xdataz	output	Turn xdata bus into ‘Z’ state
xaddr (23:0)	output	Address bus for external memories
xprgrd	output	External program memory read
xprgwr	output	External program memory write
xdatard	output	External data memory read
xdatawr	output	External data memory write
sfrdatao (7:0)	output	Data bus for user SFRs
sfrwe	output	User SFRs write enable
sfroe	output	User SFRs read
sfraddr (6:0)	output	User SFRs address bus
rxd1o	output	Serial receiver output 1
txd1	output	Serial transmitter line 1
prgaddr (15:0)	output	Internal program memory address bus
prgdatao (7:0)	output	Data bus for internal program memory
prgramwr	output	Internal program memory write
stop	output	Stop mode indicator
pmm	output	Power management mode indicator
so	output	SPI slave output
mo	output	SPI master output
scko	output	SPI clock output
scken	output	SPI clock line tri-state buffer control
sso (7:0)	output	Slave Select outputs
soen	output	SPI slave output enable
dmr (7:0)	output	RX DPRAM data input
waddrmr (10:0)	output	RX DPRAM write address
raddrmr (10:0)	output	RX DPRAM read address
enrmr	output	RX DPRAM read enable
enwmr	output	RX DPRAM write enable
txdata (3:0)	output	Ethernet transmit data
txen	output	Ethernet transmit enable
txer	output	Ethernet transmit error
dmt (7:0)	output	TX DPRAM data input
waddrmt (10:0)	output	TX DPRAM write address
raddrmt (10:0)	output	TX DPRAM read address
enrmt	output	TX DPRAM read enable
enwmt	output	TX DPRAM write enable
mdo	output	Management data output
mdc	output	Management clock
mdoe	output	Management data output enable
sxdmaddr (15:0)	output	Sync XDATA memory address bus (SXDM)
sxdmdatao (7:0)	output	Data bus for Sync XDATA memory (SXDM)
sxdmoe	output	Sync XDATA memory read (SXDM)
sxdmwe	output	Sync XDATA memory write (SXDM)