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DFP2INT

Floating Point To Integer Pipelined Converter

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    The DFP2INT is the pipelined floating point to integer converter. The input and output numbers' format has been developed according to IEEE-754 standard. The DFP2INT supports single precision real numbers and double word integers (4 Bytes). Convert operation is pipelined into 2 levels. Input data is fed every clock cycle. The first result appears after latency equal to 2 clock periods and next results are available each clock cycle. Full precision and accuracy are accomplished.
    The DFP2INT is a technology independent design, that can be implemented in a variety of process technologies.


    Family summary

    Design Standard compliance Operation Input data Output data NORMAL numbers DENORMAL, NaNs, INFINITY Pipeline levels Single clock result Initial latency
    DFPADD IEEE-754 Addition Single precision real Single precision real + + 5 + 5
    DFPMUL IEEE-754 Multiplication Single precision real Single precision real + + 7 + 7
    DFPDIV IEEE-754 Division Single precision real Single precision real + + 15 + 15
    DFPSQRT IEEE-754 Square root Single precision real Single precision real + + 9 + 9
    DFPCOMP IEEE-754 Compare Single precision real Single precision real + + 1 + 1
    DFP2INT IEEE-754 FP to Integer conversion Single precision real Integer + + 2 + 2
    DINT2FP IEEE-754 Integer to FP conversion Integer Single precision real + + 3 + 3

    The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application. Please see also the Arithmetic Coperocessors: DFPMU, DFPMU-DP and DFPAU , DFPAU-DP

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Utilized Area
    [LUT/PFU]    		 Frequency
    [MHz]
    ispXPGA -4 369/114 83

    DFP2INT implementation results for LATTICE devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-IIE -7 159 68
    SPARTAN-3 -5 179 89
    SPARTAN-3E -4 180 61
    VIRTEX-E -8 170 75
    VIRTEX-II -6 172 125
    VIRTEX-II pro -7 179 143
    VIRTEX-4 -12 140 184

    DFP2INT implementation results for XILINX devices. 
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [LC]    		 Frequency
    [MHz]
    APEX20KC -7 295 88
    STRATIX -5 245 184
    CYCLONE -6 245 165
    STRATIX II -3 185 214
    CYCLONE-II -6 265 133

    DFP2INT implementation results for ALTERA devices. 
    All features have been included. 


    Key Features
    • Full IEEE-754 compliance
    • Single precision real input numbers
    • Double word output numbers (4 Bytes)
    • Simple interface
    • No programming required
    • 2 levels pipelining
    • Full accuracy and precision
    • Results available at every clock
    • Overflow, underflow and invalid operation flags
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

    Applications

    • Math coprocessors
    • DSP algorithms
    • Embedded arithmetic coprocessor
    • Fast data processing & control

    Symbol

     datai (31:0)
    datao (31:0) 
    ofo 
    ufo 
    ifo 

    Pins description
    PinTypeDescription
    datai (31:0)inputData bus input
    datao (31:0)outputData bus output
    ofooutputOverflow flag
    ufooutputUnderflow flag
    ifooutputInvalid flag

    Block Diagram
    Argument checkerIt performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.
    datai (31:0)
    Main FP Pipelined UnitIt performs floating point to integer conversion. Gives the complex information about the results to Result Composer module.
    Result ComposerIt performs result rounding function, data alignment to IEEE-754 standard and the final flags setting.
    datao (31:0)
    ofo
    ufo
    ifo
    FP output Output bus used for data transfer

    Units
    Argument checker
    It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.
    Main FP Pipelined Unit
    It performs floating point to integer conversion. Gives the complex information about the results to Result Composer module.
    Result Composer
    It performs result rounding function, data alignment to IEEE-754 standard and the final flags setting.