Documentation
The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers' format has been developed according to IEEE-754 standard. Our solution supports single precision real number. Add operation was pipelined up to 5 levels and input data is fed every clock cycle. The first result appears after 5 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included.
Our revolutionary DFPADD is a technology independent design, that can be implemented in a variety of process technologies.
Family summary
| Design | Standard compliance | Operation | Input data | Output data | NORMAL numbers | DENORMAL, NaNs, INFINITY | Pipeline levels | Single clock result | Initial latency |
|---|---|---|---|---|---|---|---|---|---|
| DFPADD | IEEE-754 | Addition | Single precision real | Single precision real | + | + | 5 | + | 5 |
| DFPMUL | IEEE-754 | Multiplication | Single precision real | Single precision real | + | + | 7 | + | 7 |
| DFPDIV | IEEE-754 | Division | Single precision real | Single precision real | + | + | 15 | + | 15 |
| DFPSQRT | IEEE-754 | Square root | Single precision real | Single precision real | + | + | 9 | + | 9 |
| DFPCOMP | IEEE-754 | Compare | Single precision real | Single precision real | + | + | 1 | + | 1 |
| DFP2INT | IEEE-754 | FP to Integer conversion | Single precision real | Integer | + | + | 2 | + | 2 |
| DINT2FP | IEEE-754 | Integer to FP conversion | Integer | Single precision real | + | + | 3 | + | 3 |
The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application. Please see also the Arithmetic Coperocessors: DFPMU, DFPMU-DP and DFPAU , DFPAU-DP
Performance
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.
| Implementation |
Speed grade |
Utilized Area [LUT/PFU] |
Frequency [MHz] |
|---|---|---|---|
| ispXPGA | -4 | 965/294 | 43 |
DFPADD implementation results for LATTICE devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [Slices] |
Frequency [MHz] |
|---|---|---|---|
| SPARTAN-IIE | -7 | 513 | 74 |
| SPARTAN-3 | -5 | 513 | 89 |
| SPARTAN-3E | -4 | 513 | 62 |
| VIRTEX-E | -8 | 510 | 59 |
| VIRTEX-II | -6 | 513 | 127 |
| VIRTEX-II pro | -7 | 513 | 153 |
| VIRTEX-4 | -12 | 513 | 166 |
DFPADD implementation results for XILINX devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [LC] |
Frequency [MHz] |
|---|---|---|---|
| APEX20KC | -7 | 955 | 68 |
| STRATIX | -5 | 845 | 107 |
| CYCLONE | -6 | 845 | 104 |
| STRATIX II | -3 | 690 | 153 |
| CYCLONE-II | -6 | 845 | 105 |
DFPADD implementation results for ALTERA devices.
All features have been included.
Key Features
- Full IEEE-754 compliance
- Single precision real format support
- Simple interface
- No programming required
- 5 levels pipeline
- Overflow, underflow and invalid operation flags
- Full accuracy and precision
- Results available at every clock
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Applications
- Math coprocessors
- DSP algorithms
- Embedded arithmetic coprocessor
- Fast data processing & control
Symbol
adatai (31:0) bdatai (31:0)
Pins description
| Pin | Type | Description |
|---|---|---|
| adatai (31:0) | input | A data bus input |
| bdatai (31:0) | input | B data bus input |
| datao (31:0) | output | Data bus output |
| ofo | output | Overflow flag |
| ufo | output | Underflow flag |
| ifo | output | Invalid flag |
Block Diagram
| Main FP Pipelined UnitIt performs a floating point add function, giving the complex information about the results and making final flags settings. |
| Arguments CheckerIt performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. |
| Result ComposerIt performs result rounding function, data alignment to IEEE-754 standard and the final flags setting. |
datao (31:0)ofoufoifo
| FP output Output bus used for data transfer |