Digital Core Design

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D6840

Programmable Timer Module

    Documentation
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    The D6840 is a programmable timer module compatible with 6840 industry standard. It was designed designed to be used in peripheral device for D68xx processors. Moreover, our proprietary IP Core works perfect as separate module in applications where 6840 timer features are useful. The D6840 has three separate 16-bit timers, with individual control and common status registers. The timers may be used for square wave generation with duty cycle regulation. Signal may then be generated as continuous wave or single-shot mode. But this is not all, cause our unique module can be used for frequency or pulse width measurement and comparison. The D6840 has interrupt, which is useful in controlling module by CPU.
    As all of our solutions, the D6840 is a technology independent design that can be implemented in a variety of process technologies.

    Figure below shows typical connection of the D6840 to microcontroller.


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Utilized Area
    [LUT/PFU]    		 Frequency
    [MHz]
    SC -7 495/173 262
    ECP2 -7 448/192 214
    XP2 -7 448/192 145
    XP -5 433/192 130
    ECP -5 433/192 161
    EC -5 433/192 161

    D6840 implementation results for LATTICE devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-II -6 305 100
    SPARTAN-IIE -7 318 112
    SPARTAN-III -5 311 145
    SPARTAN-IIIE -5 328 166
    VIRTEX -6 341 95
    VIRTEX-E -8 318 111
    VIRTEX-II -6 254 172
    VIRTEX-IV -12 315 252
    VIRTEX-V -3 173 346

    D6840 implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [LC]    		 Frequency
    [MHz]
    CYCLONE -6 501 173
    CYCLONE-II -6 498 213
    CYCLONE-III -6 502 224
    STRATIX -5 501 168
    STRATIX-II -3 333 281
    STRATIX-III -3 330 384

    D6840 implementation results for ALTERA devices.
    All features have been included. 


    Key Features
    • Compatible with 6840 industry standard
    • Three separate timers
    • Two operation modes
      • Wave synthesis
      • Wave measurement
    • Two generation modes
      • Continuous
      • Single shot
    • Gating system for each clock input
    • Separate timer outputs
    • Prescaler mode for timer3 input clock
    • External clock or E clock used for timer decrement
    • Interrupt generation
    • Split bus for input and output data
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • External module for D68xx processors
    • Gated wave generation
    • Pulse width modulation
    • Frequency measurement and comparison
    • Pulse width measurement and comparison

    Symbol

     g3
    o3 
     c3
     datai (7:0)
     rs (2:0)
     rw
     cs0
     cs1
    irq 
    datao (7:0) 
     c1
     g1
    o1 
     c2
     g2
    o2 

    Pins description
    PinTypeDescription
    g3inputTimer 3 clock gate input
    c3inputTimer 3 external clock input
    datai (7:0)inputData bus input
    rs (2:0)inputRegister select
    rwinputRead/write control
    cs0inputChip select 0
    cs1inputChip select 1
    c1inputTimer 1 external clock input
    g1inputTimer 1 clock gate input
    c2inputTimer 2 external clock input
    g2inputTimer 2 clock gate input
    o3outputTimer 3 output
    irqoutputInterrupt request
    datao (7:0)outputData bus output
    o1outputTimer 1 output
    o2outputTimer 2 output

    Block Diagram
    Timer 3Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    g3
    o3
    C3 prescallerClock divider for C3 input. Used for divide clock by 8, in prescaled mode of timer3.
    c3
    CPU interfacePerforms access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.
    irq
    datai (7:0)
    datao (7:0)
    rs (2:0)
    rw
    cs0
    cs1
    Timer 1Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    c1
    g1
    o1
    Timer 2Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    c2
    g2
    o2
    D6840 bus Internal connections bus

    Units
    Timer 3
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    C3 prescaller
    Clock divider for C3 input. Used for divide clock by 8, in prescaled mode of timer3.
    CPU interface
    Performs access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.

    Timer 1
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    Timer 2
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.