DINT2FP
Integer to Floating Point Pipelined Converter
Documentation
The DINT2FP is the pipelined integer to floating point converter. The input numbers' format has been developed according to IEEE-754 standard. Our reliable IP Core supports double word integers (4 Bytes) and a single precision real numbers. Convert operation is pipelined to 3 levels and input data is fed every clock cycle. The first result appears after latency equal to 3 clock periods and next results are available each clock cycle. Full precision and accuracy are accomplished.
The DINT2FP is a technology independent design, that can be implemented in a variety of process technologies.
Family summary
| Design | Standard compliance | Operation | Input data | Output data | NORMAL numbers | DENORMAL, NaNs, INFINITY | Pipeline levels | Single clock result | Initial latency |
|---|---|---|---|---|---|---|---|---|---|
| DFPADD | IEEE-754 | Addition | Single precision real | Single precision real | + | + | 5 | + | 5 |
| DFPMUL | IEEE-754 | Multiplication | Single precision real | Single precision real | + | + | 7 | + | 7 |
| DFPDIV | IEEE-754 | Division | Single precision real | Single precision real | + | + | 15 | + | 15 |
| DFPSQRT | IEEE-754 | Square root | Single precision real | Single precision real | + | + | 9 | + | 9 |
| DFPCOMP | IEEE-754 | Compare | Single precision real | Single precision real | + | + | 1 | + | 1 |
| DFP2INT | IEEE-754 | FP to Integer conversion | Single precision real | Integer | + | + | 2 | + | 2 |
| DINT2FP | IEEE-754 | Integer to FP conversion | Integer | Single precision real | + | + | 3 | + | 3 |
The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application. Please see also the Arithmetic Coperocessors: DFPMU, DFPMU-DP and DFPAU , DFPAU-DP
Performance
| Implementation |
Speed grade |
Utilized Area [LUT/PFU] |
Frequency [MHz] |
|---|---|---|---|
| ispXPGA | -4 | 586/162 | 69 |
DINT2FP implementation results for LATTICE devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [Slices] |
Frequency [MHz] |
|---|---|---|---|
| SPARTAN-IIE | -7 | 189 | 69 |
| SPARTAN-3 | -5 | 190 | 88 |
| SPARTAN-3E | -6 | 190 | 63 |
| VIRTEX-E | -8 | 190 | 62 |
| VIRTEX-II | -6 | 192 | 147 |
| VIRTEX-II pro | -7 | 192 | 179 |
| VIRTEX-4 | -12 | 192 | 173 |
DINT2FP implementation results for XILINX devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [LC] |
Frequency [MHz] |
|---|---|---|---|
| APEX20KC | -7 | 470 | 87 |
| STRATIX | -5 | 400 | 150 |
| CYCLONE | -6 | 385 | 156 |
| STRATIX II | -3 | 330 | 234 |
| CYCLONE-II | -6 | 410 | 149 |
DINT2FP implementation results for ALTERA devices.
All features have been included.
Key Features
- Full IEEE-754 compliance
- Double word integer input numbers (4 Bytes)
- Single precision real output numbers
- Simple interface
- No programming required
- 3 levels pipelining
- Full accuracy and precision
- Results available at every clock
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Applications
- Math coprocessors
- DSP algorithms
- Embedded arithmetic coprocessor
- Fast data processing & control
Symbol
datai (31:0)Pins description
| Pin | Type | Description |
|---|---|---|
| datai (31:0) | input | Data bus input |
| datao (31:0) | output | Data bus output |
Block Diagram
| Main FP Pipelined UnitIt performs integer to floating point conversion, giving the complex information about the results to Result Composer module. |
| Argument checkerIt performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. |
| Result ComposerIt performs result rounding function and data alignment to IEEE-754 standard. |
datao (31:0)
| FP output Output bus used for data transfer |