Digital Core Design

DQ8051

Revolutionary Quad-Pipelined Ultra High Performance Microcontroller

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Family Summary
Performance
Info
Pins description
Block diagram
Units

DQ8051 is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memo-ries. The core has been designed with a special concern about perfor-mance to power consumption ratio. This ratio is extended, by an advanced power management PMU unit. DQ8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. DQ8051 has built-in configurable DoCD-JTAG on chip debugger, supporting Keil µVision development platform and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 19.69 to 26.62 times faster than the original 80C51 at the same frequency. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slowly, than the original implementation, for no performance penalty. DQ8051 is fully customizable, which means, that it is delivered in the exact configuration, to meet your requirements. There is no need to pay extra, for not used features and wasted silicon.

The DQ8051 is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's 8051 Core, has built in support for the DCD Hardware Debug System, called DoCD^TM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. More details about DCD on Chip Debugger

Family summary

Design	Dhry speed	on-chip CODE RAM/ROM	off-chip CODE	CODE write	IDATA space	XDATA space	XDATA, CODE wait states	DoCD^TM	PMU	Interrupt sources	DPTR	Timers	UART	IO Ports	Compare/ Capture	Watchdog	MDU MDU32	DI2CM	DI2CS	DSPI	DFPMU	DMAC	DCAN
DQ80251	56.8	8M	8M	+	1k-32k	8M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DQ8051CPU	25.13	64k/64k	64k/8M	+	256	16M	+	+	+	2	1	-	-	-	-	-	-	-	-	-	-	-	-
DQ8051	25.13	64k/64k	64k/8M	+	256	16M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DQ8051XP	26.62	64k/64k	64k/8M	+	256	16M	+	+	+	15	2	3	2	4	+	+	+	+	+	+	+	+	+
DP8051CPU	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	2	1	-	-	-	-	-	-	-	-	-	-	-	-
DP8051	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DP8051XP	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	15	2	3	2	4	+	+	+	+	+	+	+	+	+
DP80C51	11.4	64k/64k	64k	+	256	64k	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DT8051	8.1	64k/64k	64k	+	256	64k	-	+	+	11	1	2	1	1	-	-	-	-	-	-	-	-	-

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation device	Speed grade	Minimum area	Top frequency
0,35 um	typical	10500 gates	70 MHz
0,25 um	typical	11000 gates	125 MHz
0,18 um	typical	10500 gates	180 MHz
0,13 um	typical	10700 gates	260 MHz
0,09 um	typical	9900 gates	430 MHz

DQ8051 core area and performance in ASIC devices - results given for working system with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included. DoCD JTAG debugger increases core size by approximately 2 100 gates.

Implementation device	Speed grade	Minimum area	Top frequency
SPARTAN-6	-3	1900 LUT	60 MHz
VIRTEX-4	-12	2000 Slices	60 MHz
VIRTEX-5	-3	1700 LUT	110 MHz
VIRTEX-6	-3	1900 LUT	125 MHz

DQ8051 core area and performance in XILINX devices - results given for working system, with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.

Implementation device	Speed grade	Minimum area	Top frequency
CYCLONE-II	-6	3050 LC	45 MHz
CYCLONE-III	-6	3050 LC	60 MHz
CYCLONE-IV GX	-6	3050 LC	55 MHz
STRATIX-II	-3	2050 LUT	70 MHz
STRATIX-III	-2	2050 LUT	100 MHz
STRATIX-IV	-1	2050 LUT	90 MHz
STRATIX-V	-2	2050 LUT	90 MHz

DQ8051 core area and performance in ALTERA devices - results given for working system, with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.

CPU Features

software is in 100% compatible with 8051 industry standard
Quad-Pipelined architecture enables to run 26.62 times faster, than the original 80C51 at the same frequency
Up to 25.053 VAX MIPS at 100 MHz
24 times faster multiplication
12 times faster division
2 Data Pointers (DPTR) for faster memory blocks copying
- Advanced INC & DEC modes
- Auto-switch of current DPTR
Up to 256 bytes of internal (on-chip) Data Memory - IDM
Up to 64k bytes of Program Memory
Up to 16 MB of external (off-chip) Data Memory - XDM
- Synchronous interface for up to 64K bytes of (on-chip) fast external Data Memory - (SXDM)
User programmable Program Memory Wait States solution - for wide range of memories' speed
User programmable External Data Memory Wait States solution - for wide range of memories' speed
De-multiplexed Address/Data bus - to allow easy memory connection
Interface for additional Special Function Registers
Fully synthesizable
Static synchronous design
No internal tri-states
Scan test ready

Symbol

rxd0i

rxd0o

txd0

gate0

gate1

sxdmdatai

sxdmaddr

sxdmdatao

sxdmwe

sxdmoe

xdatai

xdatardy

xaddress

xdatao

xdataz

xdatawr

xdatard

prgdatai

prgrdy

prgaddr

prgdatao

prgdataz

prgrd

prgwr

port0i

port1i

port2i

port3i

port0o

port1o

port2o

port3o

stop

pmm

int0

int1

idmdatai

idmaddr

idmdatao

idmwe

idmoe

sfrdatai

sfraddr

sfrdatao

sfrwe

sfroe

tdi

tck

tms

tdo

rtck

Pins description

Pin	Type	Description
rxd0i	input	Serial receiver input 0
t0	input	Timer 0 input
t1	input	Timer 1 input
gate0	input	Timer 0 gate input
gate1	input	Timer 1 gate input
sxdmdatai	input	Synchronous External Data Memory input bus
xdatai	input	External Data Memory input bus
xdatardy	input	External Data memory ready
prgdatai	input	Program memory data input bus
prgrdy	input	Program memory ready
port0i	input	Port 0 input
port1i	input	Port 1 input
port2i	input	Port 2 input
port3i	input	Port 3 input
int0	input	External interrupt 0
int1	input	External interrupt 1
idmdatai	input	Internal Data Memory input bus
sfrdatai	input	Data bus from user SFRs
tdi	input	DoCD^TM TAP data input
tck	input	DoCD^TM TAP clock line
tms	input	DoCD^TM TAP mode select
rxd0o	output	Serial receiver output 0
txd0	output	Serial transmitter output 0
sxdmaddr	output	Synchronous External Data Memory address bus
sxdmdatao	output	Synchronous External Data Memory output bus
sxdmwe	output	Synchronous External Data Memory write enable
sxdmoe	output	Synchronous External Data Memory output enable
xaddress	output	External Data Memory address bus
xdatao	output	External Data Memory output bus
xdataz	output	Turns xdata bus into "Z" state
xdatawr	output	External Data memory write
xdatard	output	External Data memory read
prgaddr	output	Program memory address bus
prgdatao	output	Program memory data output bus
prgdataz	output	Turns prgdatao bus into "Z" state
prgrd	output	Program memory read
prgwr	output	Program memory write
port0o	output	Port 0 output
port1o	output	Port 1 output
port2o	output	Port 2 output
port3o	output	Port 3 output
stop	output	Stop mode indicator
pmm	output	Power management mode indicator
idmaddr	output	Internal Data Memory address bus
idmdatao	output	Internal Data Memory output bus
idmwe	output	Internal Data Memory write enable
idmoe	output	Internal Data Memory output enable
sfraddr	output	User SFRs address bus
sfrdatao	output	Data bus for user SFRs
sfrwe	output	User SFRs write enable
sfroe	output	User SFRs output enable
tdo	output	DoCD^TM TAP data output
rtck	output	DoCD^TM return clock

Block Diagram

Opcode decoderPerforms an opcode decoding instruction and control functions for all other blocks.

Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.

UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

rxd0i

rxd0o

txd0

TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

gate0

gate1

SXDM InterfaceSynchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.

sxdmdatai

sxdmaddr

sxdmdatao

sxdmwe

sxdmoe

External Data Memory InterfaceIt contains memory access related registers, such as Data Pointer High (DPH), Data Pointer Low (DPL), Data Page Pointer (DPP), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. It also allows applications software to access up to 16 MB of external data memory. The DPP register is used for segments swapping. STRETCH register allows flexible timing management, while accessing different speed system devices, by programming XDATAWR and XDATARD pulse width between 1 and 8 clock periods.

xdatai

xaddress

xdatao

xdataz

xdatardy

xdatawr

xdatard

ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.

Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD module.

prgdatai

prgaddr

prgdatao

prgdataz

prgrdy

prgrd

prgwr

I/O portsBlock contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3

port0i

port1i

port2i

port3i

port0o

port1o

port2o

port3o

Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.

stop

pmm

Interrupt ControllerInterrupt Controller module is responsible for the interrupt manage system of external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.

int0

int1

Internal Data Memory InterfaceInterface controls access to the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

idmdatai

idmaddr

idmdatao

idmwe

idmoe

SFR InterfaceSpecial Function Registers interface - controls access to externally connected peripherals through SFR bus.

sfrdatai

sfraddr

sfrdatao

sfrwe

sfroe

DoCD^TM JTAG DoCD^TM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD^TM debugger. The DoCD^TM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.

tdi

tck

tms

tdo

rtck

Internal data bus 8-bit internal data bus

SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Units

Opcode decoder

Performs an opcode decoding instruction and control functions for all other blocks.

Control Unit

It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.

UART0

Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

Timers

System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

SXDM Interface

Synchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.

External Data Memory Interface

It contains memory access related registers, such as Data Pointer High (DPH), Data Pointer Low (DPL), Data Page Pointer (DPP), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. It also allows applications software to access up to 16 MB of external data memory. The DPP register is used for segments swapping. STRETCH register allows flexible timing management, while accessing different speed system devices, by programming XDATAWR and XDATARD pulse width between 1 and 8 clock periods.

ALU

Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.

Program Memory Interface

Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD module.

I/O ports

Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3

Power Management Unit

Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.

Interrupt Controller

Interrupt Controller module is responsible for the interrupt manage system of external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.

Internal Data Memory Interface

Interface controls access to the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

SFR Interface

Special Function Registers interface - controls access to externally connected peripherals through SFR bus.

DoCD^TM JTAG

DoCD^TM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD^TM debugger. The DoCD^TM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.